Multiple-mask multiple-exposure lithography and masks

1. A method comprising:

forming a pattern in a material layer by using a first photomask, the first photomask including:

a first die area that includes a first portion of a first mask feature for forming an integrated circuit; and

a first stitching region disposed along a boundary of the first photomask, wherein the first stitching region includes:

a second portion of the first mask feature for forming the integrated circuit, the second portion of the first mask feature having a different width than the first portion of the first mask feature; and

a first alignment mark for in-chip overlay measurement.

2. The method of claim 1 , wherein the forming of the pattern in the material layer by using the first photomask further includes using a second photomask to form the pattern in the material layer.

3. The method of claim 1 , wherein the forming of the pattern in the material layer by using the first photomask includes performing a first exposure process using the first photomask mask to expose a first portion of the material layer; and

wherein the forming of the pattern in the material layer by using the second photomask includes performing a second exposure process using the second photomask mask to expose a second portion of the photosensitive material, wherein the second portion of the photosensitive material overlaps the first portion of the photosensitive material.

4. The method of claim 1 , wherein the first photomask further includes a a second stitching region disposed along the boundary of the first photomask, wherein the second stitching region includes a second alignment mark for in-chip overlay measurement.

5. The method of claim 4 , wherein the first alignment mark has a different shape than the second alignment mark.

6. The method of claim 1 , wherein the first alignment mark is selected from the group consisting of an inner box alignment feature, an outer box alignment feature, an inner cross alignment feature, an outer cross alignment feature, and a test line.

7. The method of claim 1 , wherein the first photomask further includes a frame area at least partially surrounding the first die area, the frame area including:

a second alignment mark for in-chip overlay measurement; and

a third alignment mark for interlevel overlay measurement.

8. A method comprising:

performing a lithography process on a material layer, wherein the performing of the lithography process includes using a first mask and a second mask,

wherein the first mask includes:

a first plurality of mask features disposed in a first die area; and

a first plurality of in-chip alignment features disposed along a boundary of the first die area, wherein the first plurality of in-chip alignment features overlap with an exposure area of a second mask and wherein the first plurality of in-chip alignment features are for overlay measurement with respect to the second mask.

9. The method of claim 8 , wherein the performing of the lithography process on the material layer includes:

performing a first exposure process using the first mask to expose a first portion of the material layer; and

performing a second exposure process using the second mask to expose a second portion of the material layer.

10. The method of claim 8 , wherein the first plurality of in-chip alignment features is disposed within a first stitching region and at least one of the mask features extends into the first stitching region.

11. The method of claim 8 , wherein the first mask further includes a second plurality of in-chip alignment features disposed along the boundary of the first die area, wherein the second plurality of in-chip alignment features overlap with an exposure area of a third mask and wherein the second plurality of in-chip alignment features are for overlay measurement with respect to the third mask.

12. The method of claim 8 , wherein the first mask further includes an interlevel alignment feature for interlevel overlay measurement.

13. The method of claim 8 , further comprising:

receiving a design layout; and

forming the first mask and the second mask based on the design layout.

14. The method of claim 8 , wherein the first mask further includes a second plurality of in-chip alignment features disposed along the boundary of the first die area, and wherein at least one in-chip alignment feature from the first plurality of in-chip alignment features interfaces with at least one in-chip alignment feature from the second plurality of in-chip alignment features.

15. The method of claim 14 , wherein the at least one in-chip alignment feature from the first plurality of in-chip alignment features includes a test line.

16. A method comprising:

using a photomask to form a semiconductor device, the photomask comprising:

a die area including a first portion of a mask feature, the first portion of the mask feature designating a functional feature of the semiconductor device; and

a stitching region disposed along an outer boundary of the mask, wherein the stitching region includes:

a second portion of the mask feature; and

a first alignment mark for in-chip overlay measurement; and

a frame area disposed along the outer boundary of the mask, wherein the frame area includes a second alignment mark for interlevel overlay measurement.

17. The method of claim 16 , wherein the second portion of the mask feature has a different shape than the first portion of the mask feature.

18. The method of claim 16 , wherein the first alignment mark is selected from the group consisting of an inner box alignment feature, an outer box alignment feature, an inner cross alignment feature, an outer cross alignment feature, and a test line.

19. The method of claim 16 , wherein the frame area further includes a third alignment mark for in-chip overlay measurement.

20. The method of claim 16 , wherein the first portion of the mask feature interfaces with the second portion of the mask feature.