SELF-PASSIVATED NITROGEN-POLAR III-NITRIDE TRANSISTOR

1 . A HEMT comprising a channel layer of a first III-Nitride semiconductor material, grown on a N-polar surface of a back barrier layer of a second III-Nitride semiconductor material; the second III-Nitride semiconductor material having a larger band gap than the first III-Nitride semiconductor material, such that a positively charged polarization interface and two-dimensional electron gas is obtained in the channel layer; a passivation, capping layer, of said first III-Nitride semiconductor material, formed on top of and in contact with a first portion of a N-polar surface of said channel layer; a gate trench traversing the passivation, capping layer, and ending at said N-polar surface of said channel layer; and a gate conductor filling said gate trench.

2 . The HEMT of claim 1 , comprising a thin layer of a third III-Nitride semiconductor material in said gate trench between said gate conductor and said N-polar surface of said channel layer.

3 . The HEMT of claim 1 , wherein said passivation, capping layer, is a layer grown on said first portion of said N-polar surface of said channel layer.

4 . The HEMT of claim 1 , wherein said first III-Nitride semiconductor material is GaN and said second III-Nitride semiconductor material is AlGaN.

5 . The HEMT of claim 2 , wherein said third III-Nitride semiconductor material is one of AlN, InAlN, AlGaN and InAlGaN.

6 . The HEMT of claim 1 , comprising a source contact layer and a drain contact layer of a fourth Ill-Nitride semiconductor, formed on a second portion of said N-polar surface of said channel layer on opposite sides of said gate trench.

7 . The HEMT of claim 6 , wherein said channel layer has a first doping level and said source and drain contact layers have a second doping level larger than the first doping level, wherein: a source access region of said passivation, capping layer, arranged between the source contact layer and the gate trench, has a third doping level comprised between the first and second doping levels; and a drain access region of said passivation, capping layer, arranged between the drain contact layer and the gate trench, has the first doping level.

8 . The HEMT of claim 6 , wherein said source contact layer and said drain contact layer are layers grown on said second portion of said N-polar surface of said channel layer.

9 . The HEMT of claim 6 , comprising a source conductor and a drain conductor in contact with respectively said source contact layer and said drain contact layer.

10 . The HEMT of claim 6 , wherein said fourth II-Nitride semiconductor material is n+ doped GaN or n+ doped InGaN.

11 . The HEMT of claim 1 , comprising: a source contact layer of a fourth III-Nitride semiconductor, formed on a second portion of said N-polar surface of said channel layer on a first side of said gate trench; and a drain contact layer of said fourth III-Nitride semiconductor, formed on a portion of a top surface of said passivation, capping layer, on a second side of said gate trench opposite said first side of said gate trench.

12 . The HEMT of claim 11 , wherein said channel layer has a first doping level and said source and drain contact layers have a second doping level larger than the first doping level, wherein: a source access region of said passivation, capping layer, arranged between the source contact layer and the gate trench, has a third doping level comprised between the first and second doping levels; and a drain access region of said passivation, capping layer, arranged between under the drain contact layer and the gate trench, has the first doping level.

13 . The HEMT of claim 11 , wherein said source contact layer and said drain contact layer are layers grown respectively on said second portion of said N-polar surface of said channel layer and on said portion of a top surface of said capping layer.

14 . The HEMT of claim 11 , comprising a source conductor and a drain conductor in contact with respectively said source contact layer and said drain contact layer.

15 . The HEMT of claim 6 , wherein said fourth III-Nitride semiconductor material is n+ doped GaN or n+ doped InGaN.

16 . The HEMT of claim 1 , wherein a gate insulator layer lines the side and bottom of said gate conductor in said trench.