Memory cell structure with capacitor over transistor

1. A memory cell structure comprising:

a silicon substrate with a silicon surface;

a transistor coupled to the silicon surface; comprising a gate structure, a first conductive region, and a second conductive region;

a bit line electrically coupled to the first conductive region of the transistor and positioned under the silicon surface;

a capacitor over the transistor and electrically coupled to the second conductive region of the transistor, wherein a lower electrode of the capacitor directly covers a top side of the gate structure of the transistor; and

a first spacer covering a first side of the gate structure and positioned above the silicon surface; and a second spacer covering a second side of the gate structure and positioned above the silicon surface; wherein the first conductive region of the transistor extends upward from the silicon surface and abuts against the first spacer, and the second conductive region of the transistor extends upward from the silicon surface and abuts against the second spacer.

2. The memory cell structure of claim 1 , wherein the capacitor encompasses at least a top side and a sidewall of the transistor.

3. The memory cell structure of claim 1 , wherein the bit line is electrically coupled to the first conductive region of the transistor through a bridge contact, the bridge contact is positioned under the silicon surface and a first sidewall of the bridge contact is aligned with an edge of the bit line, and the bridge contact comprises an upper portion and a lower portion, the upper portion of the bridge contact abuts against the silicon substrate, and the lower portion of the bridge contact is separated from the silicon substrate by a first isolating layer.

4. The memory cell structure of claim 1 , further comprising:

a word line extended beyond the transistor and coupled to the gate structure of the transistor, wherein the word line comprises an upper portion which is above the silicon surface, and a sidewall of the upper portion of the word line is aligned with a sidewall of the gate structure.

5. The memory cell structure of claim 4 , wherein the transistor further comprises a dielectric layer encompassing the word line and the gate structure.

6. The semiconductor device structure of claim 5 , wherein at least part of the gate structure extends downward from the silicon surface.

7. A memory cell structure comprising:

a silicon substrate with a silicon surface;

a transistor coupled to the silicon surface; comprising a gate structure, a first conductive region, a second conductive region;

a bit line electrically coupled to the first conductive region of the transistor, wherein the bit line is positioned under the silicon surface and electrically coupled to the first conductive region of the transistor through a bridge contact, and the bridge contact is positioned under the silicon surface and a first sidewall of the bridge contact is aligned with an edge of the bit line; and

a capacitor electrically coupled to the second conductive region of the transistor and encompassing the transistor.

8. The memory cell structure of claim 7 , wherein the capacitor comprises a first portion vertically stacked above a top side of the transistor and second portion abutted against a sidewall of the transistor.

9. The memory cell structure of claim 7 , wherein the bridge contact comprises an upper portion and a lower portion, the upper portion of the bridge contact abuts against the silicon substrate, and the lower portion of the bridge contact is separated from the silicon substrate by a first isolating layer.

10. The memory cell structure of claim 9 , wherein the first isolating layer at least covers a first sidewall, a second sidewall and a bottom of the lower portion of the bridge contact.

11. The memory cell structure of claim 9 , wherein the upper portion of the bridge contact comprises a metal region and a doped semiconductor region surrounding the metal region, and the doped semiconductor region abuts against the silicon substrate.

12. The memory cell structure of claim 7 , wherein the bridge contact is positioned under the silicon surface and a first dielectric cap covers a top surface of the bridge contact.

13. The memory cell structure of claim 12 , wherein the transistor further comprises a first spacer and a second spacer, the first spacer covering a first side of the gate structure and positioned above the silicon surface, and the second spacer covering a second side of the gate structure and positioned above the silicon surface; wherein the first conductive region of the transistor extends upward from the silicon surface and abuts against the first spacer, and the second conductive region of the transistor extends upward from the silicon surface and abuts against the second spacer.

14. The memory cell structure of claim 13 , further comprising:

a second dielectric cap covering a top surface of the first conductive region of the transistor.

15. A memory cell structure comprising:

a silicon substrate with a silicon surface;

a transistor coupled to the silicon surface; comprising a gate structure, a first conductive region, a second conductive region, a dielectric cap, and a spacer, wherein the dielectric cap is vertically stacked on the gate structure, the spacer covers a side wall of the gate structure, and the second conductive region of the transistor extends upward from the silicon surface and abuts against the spacer; and

a capacitor over the transistor and coupled to the second conductive region of the transistor, wherein the capacitor comprises a first portion and a second portion, the first portion of the capacitor is vertically positioned on the dielectric cap and the second portion of the capacitor abuts against the second conductive region;

wherein a planar size of the memory cell structure is smaller than 10 times λ 2 , wherein λ is a minimum feature size and the minimum feature size is equal to or below 10 nm.

16. A memory cell structure formed between a bridge contact and an isolation trench, the bridge contact and at least a portion of the isolation trench being under a silicon surface of a silicon substrate, and the memory cell structure coupled to a word line and a bit line, the memory cell structure comprising:

a transistor coupled to the silicon surface; comprising a gate structure, a first conductive region, a second conductive region; and

a capacitor over the transistor and coupled to the second conductive region of the transistor;

wherein the bit line is disposed under the silicon surface and a lower portion of the bridge contact abuts against the bit line, an upper portion of the bridge contact abuts against portion of the silicon substrate, and a first sidewall of the bridge contact is aligned with a lateral edge of the bit line.

17. The memory cell structure of claim 16 , wherein the word line extends beyond the transistor and coupled to the gate structure of the transistor, the word line comprises an upper portion which is above the silicon surface and a sidewall of an upper portion of an interconnection line is aligned with a sidewall of the gate structure.

18. The memory cell structure of claim 17 , wherein the capacitor further comprises a metal electrode, a first portion of the metal electrode is vertically positioned on the isolation trench.

19. The memory cell structure of claim 18 , wherein the capacitor further comprises a dielectric layer encompassed by the metal electrode, a first portion of the dielectric layer abuts against the second conductive region and the first portion of the metal electrode.

20. The memory cell structure of claim 19 , wherein an extension direction of the first portion of the metal electrode is parallel to a normal direction of the silicon substrate, an extension direction of the first portion of the dielectric layer is parallel to the normal direction of the silicon substrate, and an extension direction of the second conductive region is parallel to the normal direction of the silicon substrate.