Multi-level memristor elements
There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element.
1. A two-terminal multi-level memristor comprising:
a first set of resistance elements comprising a plurality of resistance elements connected in series between first and second terminals of the multi-level memristor; and
a second set of resistance elements comprising a plurality of second resistance elements, wherein each of the resistance elements of the second set is connected in parallel with a different number of one or more of the series connected resistance elements of the first set,
wherein one of the first set and second set of resistance elements comprises a plurality of binary memristors that can be selectively programmed to either a high or low resistance state and the other of the first and second set of resistance elements comprises a plurality of shunt resistors.
2. The multi-level memristor element of claim 1 , wherein the first set of resistance elements comprises said plurality of binary memristors and second set of resistance elements comprises said plurality of shunt resistors.
3. The multi-level memristor element of claim 1 , wherein the first set of resistance elements comprises said plurality of shunt resistors and second set of resistance elements comprises said plurality of binary memristors.
4. The multi-level memristor element of claim 3 , wherein the first set of resistance elements further comprises a binary memristor.
5. The multi-level memristor element of claim 1 , wherein the first set of resistance elements further comprises a resistance element which is not in parallel with any of the resistance elements of the second set of resistance elements.
6. The multi-level memristor element of claim 1 , wherein the first set of resistance elements further comprises an offset resistor.
7. The multi-level memristor element of claim 1 , wherein each of the resistance elements of the second set of resistance elements is connected, on one side, to a common node.
8. The multi-level memristor element of claim 7 , wherein said common node is one of the two terminals of the two-terminal multi-level memristor.
9. The multi-level memristor element of claim 1 , wherein the first and second sets of resistance elements are configured such that a resultant change in overall resistance of the two-terminal multi-level memristor as a result of varying the resistance state of one of the binary memristors between the high and low resistance states is different for each of the binary memristors.
10. The multi-level memristor element of claim 9 , wherein the resultant changes in overall resistance of the two-terminal multi-level memristor as a result of varying the resistance state of the binary memristors is scaled to provide a binary coding.
11. The multi-level memristor element of claim 1 , wherein each of the plurality of binary memristors has substantially the same resistance characteristics.
12. The multi-level memristor element of claim 1 , further comprising switching circuitry, the switching circuitry configured to apply electrical control signal to selectively program said binary memristors to either of a high resistance or a low resistance state.
13. The multi-level memristor element of claim 11 , further comprising a controller configured to receive an input data value to be applied using the two-terminal multi-level memristor element, wherein the controller is configured to control the switching circuitry to program the binary memristors based on the input data value.
14. The multi-level memristor element of claim 13 , wherein the controller is configured to control the programming of the binary memristors based on the input data value such that a variation in the input data value leads to a variation in conductance of the two-terminal multi-level memristor which varies linearly with the input data value.
15. An analogue computing circuit comprising the two-terminal multi-level memristor of claim 1 .
16. A synapse circuit for a neural network comprising at least one two-terminal multi-level memristor as claimed in claim 1 .
17. The synapse circuit of claim 16 , wherein the synapse circuit comprises:
an input to receive at least one data input signal indicative of a data input, the data input signal provided as a voltage or current;
an output to provide at least one data output current indicative of the data input times a defined weighting value; and
at least first and second data paths between the input and the output, each of said data paths comprising one of said at least one two-terminal multi-level memristor,
wherein the at least one data input signal is applied to at least one of the data paths,
wherein the resistance level of at least one multi-level memristor is adjusted based on the defined weighting value, and
wherein the data output current is based on the current through said at least first and second data paths.
18. A two-terminal multi-level memristor element comprising:
a plurality of first resistance elements connected in series between first and second terminals of the multi-level memristor element; and
a plurality of second resistance elements, wherein each of the second resistance elements is connected in parallel with a different number of one or more of the series connected first resistance elements,
wherein one of the first and second resistance elements comprise binary memristors that can be selectively programmed to either a high or low resistance state and the other of the first and second resistance elements comprise shunt resistors.
19. The two-terminal multi-level memristor element of claim 1 , wherein the first resistance elements comprise said binary memristors and the second resistance elements comprise said shunt resistors.
20. A two-terminal memristor apparatus which is programmable to provide more than two different define resistance values between the two terminals, the apparatus comprising:
a first set of a plurality of resistance elements connected in series between the two terminals of the multi-level memristor apparatus; and
a second set of a plurality of resistance elements which are nested in parallel with different numbers of resistance elements of the first set,
wherein at least some of the resistance elements of the first and second sets comprise binary memristors that can be selectively programmed to either a high or low resistance state and at least some of the resistance elements of the first and second sets comprise non-programmable resistors.