Imaging device and electronic apparatus
An imaging device according to the present disclosure has a stacked chip structure in which at least two semiconductor chips, that are a first semiconductor chip provided with a pixel circuit and a second semiconductor chip including an analog-to-digital (AD) conversion circuit which is provided so as to correspond to the pixel circuit, are stacked. The AD conversion circuit includes a latch circuit that retains a digital code after AD conversion and a transfer circuit that transfers the digital code after AD conversion. Further, a failure detection circuit for detecting a failure of the AD conversion circuit is provided. The failure detection circuit performs failure detection by writing a test pattern for failure detection into the latch circuit via the transfer circuit, then reading the test pattern from the latch circuit via the transfer circuit, and comparing the read test pattern with an expected value.
1. An imaging device, comprising:
a stacked chip structure that includes at least two semiconductor chips, wherein
the at least two semiconductor chips include a first semiconductor chip and a second semiconductor chip,
the first semiconductor chip includes a pixel circuit,
the pixel circuit includes a photoelectric conversion element,
the second semiconductor chip includes an analog-to-digital conversion circuit corresponding to the pixel circuit,
the analog-to-digital conversion circuit configured to execute analog-to-digital conversion on a specific signal, and
the analog-to-digital conversion circuit includes:
a latch circuit configured to retain a digital code after the analog-to-digital conversion; and
a transfer circuit configured to transfer the digital code after the analog-to-digital conversion; and
a failure detection circuit configured to:
write, via the transfer circuit, a test pattern for failure detection to the latch circuit, wherein
the test pattern is a toggle pattern in which logic of an alternating pattern is inverted in synchronization with a clock signal,
the clock signal is for generation of the test pattern, and
the alternating pattern is a pattern in which logic “1” and logic “0” have an alternate arrangement;
read, via the transfer circuit, the test pattern from the latch circuit;
compare the read test pattern with a specific value; and
detect failure of the analog-to-digital conversion circuit based on a result of the comparison.
2. The imaging device according to claim 1 , wherein
the pixel circuit is configured to output a signal level and a reset level,
the analog-to-digital conversion circuit is further configured to:
execute analog-to-digital conversion on the signal level to obtain D-phase data; and
execute analog-to-digital conversion on the reset level to obtain P-phase data,
the latch circuit includes a latch circuit for test-pattern writing, a latch circuit for P-phase reading, and a latch circuit for D-phase reading, and
the transfer circuit includes a transfer circuit for test-pattern writing, a transfer circuit for P-phase reading, and a transfer circuit for D-phase reading.
3. The imaging device according to claim 2 , wherein the failure detection circuit is further configured to:
write the test pattern to the latch circuit for test-pattern writing via the transfer circuit for test-pattern writing;
read the test pattern from the latch circuit for P-phase reading via the transfer circuit for P-phase reading;
write, after the test pattern is read from the latch circuit for P-phase reading, the test pattern to the latch circuit for test-pattern writing via the transfer circuit for test-pattern writing; and
read the test pattern from the latch circuit for D-phase reading via the transfer circuit for D-phase reading.
4. The imaging device according to claim 3 ,
wherein the failure detection circuit is further configured to execute expected-value comparison to assess whether the test pattern read from the latch circuit for P-phase reading via the transfer circuit for P-phase reading and the test pattern read from the latch circuit for D-phase reading via the transfer circuit for D-phase reading agree with the specific value.
5. The imaging device according to claim 4 , wherein the failure detection circuit is further configured to execute the expected-value comparison within a vertical blanking period.
6. The imaging device according to claim 1 , wherein
the transfer circuit is divided into a plurality of groups in a unit of a determined number,
the failure detection circuit is further configured to:
execute failure detection for the transfer circuit; and
partially execute failure detection for each group of the plurality of groups based on the execution of the failure detection of the transfer circuit.
7. An electronic apparatus, comprising:
an imaging device that includes:
a stacked chip structure that includes at least two semiconductor chips, wherein
the at least two semiconductor chips include a first semiconductor chip and a second semiconductor chip,
the first semiconductor chip includes a pixel circuit,
the pixel circuit includes a photoelectric conversion element,
the second semiconductor chip includes an analog-to-digital conversion circuit corresponding to the pixel circuit,
the analog-to-digital conversion circuit configured to execute analog-to-digital conversion on a specific signal, and
the analog-to-digital conversion circuit includes:
a latch circuit configured to retain a digital code after the analog-to-digital conversion; and
a transfer circuit configured to transfer the digital code after the analog-to-digital conversion; and
a failure detection circuit configured to:
write, via the transfer circuit, a test pattern for failure detection to the latch circuit, wherein
the test pattern is a toggle pattern in which logic of an alternating pattern is inverted in synchronization with a clock signal,
the clock signal is for generation of the test pattern, and
the alternating pattern is a pattern in which logic “1” and logic “0” have an alternate arrangement;
read, via the transfer circuit, the test pattern from the latch circuit;
compare the read test pattern with a specific value; and
detect failure of the analog-to-digital conversion circuit based on a result of the comparison.
8. An imaging device, comprising:
a stacked chip structure that includes at least two semiconductor chips, wherein
the at least two semiconductor chips include a first semiconductor chip and a second semiconductor chip,
the first semiconductor chip includes a pixel circuit,
the pixel circuit includes a photoelectric conversion element,
the pixel circuit is configured to output a signal level and a reset level,
the second semiconductor chip includes an analog-to-digital conversion circuit corresponding to the pixel circuit,
the analog-to-digital conversion circuit configured to execute analog-to-digital conversion on each of:
the signal level to obtain D-phase data, and
the reset level to obtain P-phase data, and
the analog-to-digital conversion circuit includes:
a latch circuit configured to retain a digital code after the analog-to-digital conversion, wherein the latch circuit includes a latch circuit for test-pattern writing, a latch circuit for P-phase reading, and a latch circuit for D-phase reading; and
a transfer circuit configured to transfer the digital code after the analog-to-digital conversion, wherein the transfer circuit includes a transfer circuit for test-pattern writing, a transfer circuit for P-phase reading, and a transfer circuit for D-phase reading; and
a failure detection circuit configured to:
write, via the transfer circuit for test-pattern writing, a test pattern for failure detection to the latch circuit for test-pattern writing;
read, via the transfer circuit for P-phase reading, the test pattern from the latch circuit for P-phase reading;
compare the read test pattern with a specific value; and
detect failure of the analog-to-digital conversion circuit based on a result of the comparison.
9. An imaging device, comprising:
a stacked chip structure that includes at least two semiconductor chips, wherein
the at least two semiconductor chips include a first semiconductor chip and a second semiconductor chip,
the first semiconductor chip includes a pixel circuit,
the pixel circuit includes a photoelectric conversion element,
the second semiconductor chip includes an analog-to-digital conversion circuit corresponding to the pixel circuit,
the analog-to-digital conversion circuit configured to execute analog-to-digital conversion on a specific signal, and
the analog-to-digital conversion circuit includes:
a latch circuit configured to retain a digital code after the analog-to-digital conversion; and
a transfer circuit configured to transfer the digital code after the analog-to-digital conversion, wherein
the transfer circuit is divided into a plurality of groups in a unit of a determined number; and
a failure detection circuit configured to:
write, via the transfer circuit, a test pattern for failure detection to the latch circuit;
read, via the transfer circuit, the test pattern from the latch circuit;
compare the read test pattern with a specific value;
execute failure detection of the transfer circuit based on a result of the comparison; and
partially execute failure detection for each group of the plurality of groups when the failure detection of the transfer circuit is executed.