Integrated circuit device and method

1. An integrated circuit (IC) device, comprising:

a substrate;

a cell over the substrate, the cell comprising:

at least one active region;

at least one gate region extending across the at least one active region; and

at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to external circuitry outside the cell;

a metal-zero (M 0 ) layer over the at least one gate region; and

an upper metal layer over the M 0 layer,

wherein

the at least one IO pattern extends obliquely to both the at least one active region and the at least one gate region,

the M 0 layer comprises at least one M 0 conductive pattern electrically coupled to the at least one active region or the at least one gate region, and

the upper metal layer comprises the at least one IO pattern electrically coupled to the at least one M 0 conductive pattern.

2. The IC device of claim 1 , wherein

the at least one active region is elongated along a first axis, and

the at least one gate region is elongated along a second axis transverse to the first axis.

3. The IC device of claim 1 , wherein

the upper metal layer is a metal-one (M 1 ) layer.

4. The IC device of claim 1 , wherein

the at least one active region comprises first and second active regions,

the first and second active regions extend along a first axis, and are directly adjacent each other along a second axis transverse to the first axis, and

the M 0 layer has no more than three rows of M 0 conductive patterns over and between the first and second active regions, the rows of M 0 conductive patterns extending along the first axis and directly adjacent each other along the second axis.

5. The IC device of claim 1 , wherein

the at least one active region comprises first and second active regions,

the first and second active regions extend along a first axis, and are directly adjacent each other along a second axis transverse to the first axis, and

the M 0 layer has

a first row of one or more M 0 conductive patterns over the first active region, the first row extending along the first axis, and

a second row of one or more M 0 conductive patterns over the second active region, the second row extending along the first axis and directly adjacent the first row along the second axis.

6. The IC device of claim 1 , wherein

the at least one active region comprises first, second and third active regions, the second active region arranged between the first and third active regions,

the IC device further comprises:

first, second and third contact structures over and in electrical contact with corresponding source/drain regions correspondingly in the first, second and third active regions; and

an extended contact structure over and electrically coupled to the first and third contact structures, the extended contact structure extending over the second contact structure without being electrically coupled to the second contact structure, and

the M 0 layer is over the first, second and third contact structures, and the extended contact structure.

7. The IC device of claim 1 , wherein

the cell further comprises at least one dummy gate region, and

the at least one IO pattern extends obliquely to and overlaps the at least one dummy gate region.

8. A method, comprising:

generating a layout diagram of a first cell of an integrated circuit (IC) device, said generating the layout diagram of the first cell comprising:

arranging, in a first boundary, at least one gate region across at least one active region, and

arranging, in a second boundary, at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to external circuitry outside the first cell,

wherein a first edge of the first boundary and a second edge of the second boundary overlap each other and form therebetween an acute angle; and

storing the generated layout diagram on a non-transitory computer-readable medium.

9. The method of claim 8 , wherein

the at least one active region extends along a first axis,

the at least one gate region extends along a second axis transverse to the first axis,

the first edge of the first boundary extends along the second axis, and

the second edge of the second boundary extends along a third axis oblique to both the first axis and the second axis.

10. The method of claim 8 , wherein

the first boundary is rectangular, and

the second boundary is hexagonal.

11. The method of claim 8 , wherein

the at least one IO pattern is parallel to the second edge of the second boundary.

12. The method of claim 8 , wherein

the second boundary is a convex hexagon.

13. The method of claim 8 , wherein

the second boundary is a concave hexagon having one internal corner greater than 180 degrees, and five internal corner smaller than 180 degrees.

14. The method of claim 8 , wherein

the second boundary is a concave hexagon having two internal corner greater than 180 degrees, and four internal corner smaller than 180 degrees.

15. The method of claim 8 , further comprising:

generating an IC layout diagram, said generating the IC layout diagram comprising placing the first and second boundaries of the first cell in abutment with corresponding first and second boundaries of a second cell in the IC layout diagram.

16. The method of claim 15 , wherein

in said placing, the second boundary of the first cell is placed in abutment with the corresponding second boundary of the second cell along a common edge, and

the common edge is oblique to the at least one gate region in the first cell.

17. The method of claim 15 , wherein

the second boundary of the second cell has a shape of a rectangle, an isosceles trapezoid, a rhombus, a hexagon, or a combination of more than one hexagons.

18. A method, comprising:

forming at least one gate region across at least one active region over a substrate;

depositing and patterning, in a metal layer over the at least one gate region, a conductive pattern overlapping and electrically coupled to the at least one active region or the at least one gate region; and

depositing and patterning, in a pin access layer over the metal layer, an input/output (IO) pattern overlapping and electrically coupled to the conductive pattern, wherein the IO pattern and the at least one gate region form an acute angle therebetween.

19. The method of claim 18 , further comprising:

forming the at least one active region including first, second and third active regions, the second active region arranged between the first and third active regions;

depositing and patterning first, second and third contact structures over and in electrical contact with corresponding source/drain regions correspondingly in the first, second and third active regions; and

depositing and patterning an extended contact structure over and electrically coupled to the first and third contact structures, the extended contact structure extending over the second contact structure without being electrically coupled to the second contact structure,

wherein the metal layer is over the first, second and third contact structures, and the extended contact structure.

20. The method of claim 18 , further comprising:

forming at least one dummy gate region,

wherein the at least one IO pattern extends obliquely to and overlaps the at least one dummy gate region.