Chip warpage reduction via raised free bending and re-entrant (auxetic) trace geometries
View Patent ↗A microelectronic device and method of making the same including a substrate and at least one expansion layer that adds stress to the substrate when said substrate expands.
1. A transformer comprising:
a transformer having a plurality of passive copper layers;
each of said copper layers having a perimeter;
each of said copper layers including an expansion layer thereon; and
wherein when each of said passive copper layers expand, said expansion layers become thicker perpendicular to a direction of expansion.
2. The transformer of claim 1 wherein said expansion layers include at least one pattern comprised of an auxetic shape.
3. The transformer of claim 1 wherein said expansion layers include a pattern of auxetic shapes on said perimeter of said passive copper layers.
4. The transformer of claim 1 wherein said expansion layers include a pattern of auxetic shapes on said perimeter of said passive copper layers, said pattern of auxetic shapes surround areas having no patterns of auxetic shapes.
5. A method of reducing the warpage of passive copper layers having a perimeter in a transformer comprising the steps of: forming an expansion layer on said passive copper layers wherein when said passive copper layers expand said expansion layers become thicker perpendicular to a direction of expansion.
6. The method of claim 5 wherein said expansion layers include at least one pattern comprised of an auxetic shape.
7. The method of claim 5 wherein said expansion layers include a pattern of auxetic shapes on the perimeter of said passive copper layers.
8. The method of claim 5 wherein said expansion layers include a pattern of auxetic shapes on the perimeter of said passive copper layers, said pattern of auxetic shapes surround areas having no patterns of auxetic shapes.