Electroplated indium bump stacks for cryogenic electronics
A cryogenic under bump metallization (UBM) stack includes an adhesion and barrier layer and a conductive pillar on the adhesion and barrier layer. The conductive pillar functions as a solder wetting layer of the UBM stack and has a thickness. An indium superconducting solder bump is on the conductive pillar. The thickness of the conductive pillar is sufficient to prevent intermetallic regions, which form in the conductive pillar at room temperature due to interdiffusion, from extending through the entire thickness of the conductive pillar to maintain the structural integrity of the UBM stack. The indium (In) solder bump may be formed through electroplating, with the conductive pillar being copper (Cu) and the adhesion and barrier layer being titanium tungsten (TiW) and a thin seed layer of copper (Cu), or a layer of titanium (Ti).
1. A cryogenic under bump metallization (UBM) stack, comprising:
a bond pad;
an adhesion and barrier layer formed on the bond pad;
a conductive pillar on the adhesion and barrier layer, the conductive pillar configured to function as a solder wetting layer of the UBM stack and having a thickness; and
an indium superconducting solder bump on the conductive pillar, the thickness of the conductive pillar being sufficient to prevent intermetallic regions in the conductive pillar that form due to interdiffusion between the conductive pillar and the indium superconducting solder bump during heat treatments and storage at room temperature from extending through the thickness of the conductive pillar.
2. The cryogenic UBM stack of claim 1 , wherein the adhesion and barrier layer comprises a layered structure including a plurality of layers.
3. The cryogenic UBM stack of claim 2 , wherein the layered structure has a layer of tungsten titanium (TiW) and a thin seed layer of copper (Cu).
4. The cryogenic UBM stack of claim 3 , wherein the layer of TiW has a thickness of 100-150 nm and the thin seed layer of Cu has a thickness of 100-200 nm.
5. The cryogenic UBM stack of claim 1 , wherein the conductive pillar is copper (Cu).
6. The cryogenic UBM stack of claim 5 , wherein the thickness of the Cu pillar is at least 5 μm.
7. The cryogenic UBM stack of claim 1 , wherein the adhesion and barrier layer is a titanium (Ti) layer.
8. The cryogenic UBM stack of claim 1 , wherein adhesion and barrier layer may be selectively removed relative to the indium superconducting solder bump.
9. A cryogenic electronic chip, comprising:
a semiconductor die including a bond pad; and
an under bump metallization (UBM) stack on semiconductor die, the UBM stack including:
an adhesion and barrier layer on the bond pad;
a conductive pillar on the adhesion and barrier layer, the conductive pillar being a solder wetting layer of the UBM stack and having a thickness; and
an indium superconducting solder bump on the conductive pillar, the thickness of the conductive pillar having a value great enough to prevent intermetallic regions in the conductive pillar that form due to interdiffusion between the conductive pillar and the indium superconducting solder ball during heat treatments and storage at room temperature from extending through the thickness of the conductive pillar to the adhesion and barrier layer.
10. The cryogenic electronic chip of claim 9 , wherein the adhesion and barrier layer is a layer of tungsten titanium (TiW) and a thin seed layer of copper (Cu) and the conductive pillar is copper (Cu).
11. The cryogenic electronic chip of claim 10 , wherein the heat treatments include multiple temperature variations up to a maximum of 200° C. and wherein the UBM stack can maintain mechanical and electrical integrity when subjected to cryogenic shocks from room temperature to 4 K subsequent to the heat treatments and storage at room temperature.