Ultraviolet radiation shield layer
A method is provided to fabricate a wafer including a bonding layer interposed between a device wafer and a handle wafer. The method includes performing a first deposition process to deposit an ultraviolet (UV) shield layer on a backside surface of the handle wafer. A second deposition process is performed to deposit a stress compensation layer on an exposed surface of the UV shield layer. The UV shield layer blocks UV energy generated while performing the second deposition process from reaching the bonding layer.
1. A method of fabricating a wafer, the method comprising:
performing a first deposition process on a wafer stack, the wafer stack including a bonding layer interposed between a device wafer and a handle wafer;
depositing an ultraviolet (UV) shield layer on a backside surface of the handle wafer according to the first deposition process; and
performing a second deposition process on the wafer stack to deposit a stress compensation layer on an exposed surface of the UV shield layer,
wherein the UV shield layer blocks UV energy generated while performing the second deposition process from reaching the bonding layer.
2. The method of claim 1 , wherein the UV shield layer completely covers the backside surface of the handle wafer.
3. The method of claim 1 , wherein the stress compensation layer completely covers the exposed surface of the UV shield layer.
4. The method of claim 1 , wherein the first and second deposition processes each include a physical vapor deposition (PVD) process.
5. The method of claim 4 , wherein the UV shield layer comprises tantalum (Ta).
6. The method of claim 5 , wherein the UV shield layer has a thickness of at least 0.1 μm.
7. The method of claim 5 , wherein the stress compensation layer comprises silicon dioxide (SiO 2 ).
8. The method of claim 7 , wherein the bonding layer includes an adhesive comprising an organic material, the adhesive configured to maintain bonding at a temperature ranging from about 250 degrees Celsius (° C.) to about 300° C.
9. The method of claim 8 , wherein the UV shield layer prevents the bonding layer from curing while depositing the stress compensation layer.
10. A method of fabricating a wafer, the method comprising:
performing a first deposition process on a wafer stack, the wafer stack including a bonding layer interposed between a device wafer and a handle wafer;
depositing an ultraviolet (UV) shield layer on a backside surface of the handle wafer according to the first deposition process;
performing a second deposition process on the wafer stack to deposit a stress compensation layer on an exposed surface of the UV shield layer,
blocking UV energy generated from reaching the bonding layer using the UV shield layer while depositing the stress compensation layer; and
flexing the wafer stack in response to depositing the stress compensation layer.
11. The method of claim 10 , wherein flexing the wafer stack includes flexing the wafer stack from a bowed profile to a substantially straight profile.
12. The method of claim 11 , wherein blocking UV energy is performed simultaneously with flexing the wafer stack.
13. The method of claim 12 , wherein the stress compensation layer applies a stress to the wafer stack so as to strain the wafer stack into the substantially straight profile.
14. The method of claim 10 , wherein the UV shield layer completely covers the backside surface of the handle wafer.
15. The method of claim 10 , wherein the stress compensation layer completely covers the exposed surface of the UV shield layer.
16. The method of claim 10 , wherein the first and second deposition processes each include a physical vapor deposition (PVD) process.
17. The method of claim 16 , wherein the UV shield layer comprises tantalum (Ta), and wherein the stress compensation layer comprises silicon dioxide (SiO 2 ).
18. The method of claim 10 , wherein the bonding layer includes an adhesive comprising an organic material, and the UV shield layer prevents the adhesive from curing while depositing the stress compensation layer.
19. A semiconductor device comprising:
a wafer stack including a bonding layer interposed between a device wafer and a handle wafer;
an ultraviolet (UV) shield layer on a backside surface of the handle wafer; and
a stress compensation layer on an exposed surface of the UV shield layer,
wherein the UV shield layer is configured to block UV energy from reaching the bonding layer.
20. The semiconductor device of claim 19 , wherein the UV shield layer comprises tantalum (Ta), and wherein the stress compensation layer comprises silicon dioxide (SiO 2 ).