Inner filler layer for multi-patterned metal gate for nanostructure transistor

1. A method, comprising:

forming an inter-sheet filler layer between first semiconductor nanostructures of a first nanostructure transistor and between second semiconductor nanostructures of a second nanostructure transistor;

removing the inter-sheet filler layer from between the first semiconductor nanostructures;

forming a first gate metal layer between the first semiconductor nanostructures and on the second semiconductor nanostructures while the inter-sheet filler layer is between the second semiconductor nanostructures;

removing the first gate metal layer and the inter-sheet filler layer from the second semiconductor nanostructures; and

forming a second gate metal layer between the second semiconductor nanostructures and on the first gate metal layer over the first semiconductor nanostructures.

2. The method of claim 1 , wherein the first nanostructure transistor has a first threshold voltage, and the second nanostructure transistor has a second threshold voltage different than the first threshold voltage.

3. The method of claim 1 , further comprising:

forming the inter-sheet filler layer between third semiconductor nanostructures of a third nanostructure transistor;

forming the first gate metal layer while the inter-sheet filler layer is between the third semiconductor nanostructures;

forming the second gate metal layer while the inter-sheet filler layer is between the third semiconductor nanostructures;

removing the first gate metal layer, the second gate metal layer, and the inter-sheet filler layer from the third semiconductor nanostructures; and

forming a third gate metal layer between the third semiconductor nanostructures and on the second gate metal layer over the first and second semiconductor nanostructures.

4. The method of claim 3 , wherein the first nanostructure transistor has a first threshold voltage, the second nanostructure transistor has a second threshold voltage different than the first threshold voltage, and the third nanostructure transistor has a third threshold voltage different than the first and second threshold voltages.

5. The method of claim 1 , further comprising forming a gate dielectric layer on the first and second semiconductor nanostructures prior to forming the inter-sheet filler layer.

6. The method of claim 5 , wherein forming the inter-sheet filler layer between the first and second semiconductor nanostructures includes forming the inter-sheet filler layer on the gate dielectric layer.

7. The method of claim 1 , further comprising removing the inter-sheet filler layer from sides of the first and second semiconductor nanostructures prior to forming the first gate metal layer.

8. The method of claim 7 , wherein removing the inter-sheet filler layer from sides of the first and second semiconductor nanostructures includes performing an anisotropic etch.

9. The method of claim 7 , wherein removing the inter-sheet filler layer from sides of the first and second semiconductor nanostructures includes performing a sidewall conversion treatment on side portions of the inter-sheet filler layer on the sides of the first and second semiconductor nanostructures and selectively etching the side portions with respect to portions of the inter-sheet filler layer between the first semiconductor nanostructures and between the second semiconductor nanostructures.

10. The method of claim 9 , wherein selectively etching includes performing a wet etch.

11. The method of claim 1 , wherein the inter-sheet filler layer includes silicon.

12. The method of claim 1 , wherein the first and second gate metal layers are different materials.

13. An integrated circuit, comprising:

a first nanostructure transistor including a plurality of first semiconductor nanostructures;

a second nanostructure transistor including a plurality of second semiconductor nanostructures;

an inter sheet filler layer between the second semiconductor nanostructures;

a first gate metal layer between the first semiconductor nanostructures and on sides of the second semiconductor nanostructures; and

a second gate metal layer on the first gate metal layer on the first and second semiconductor nanostructures.

14. The integrated circuit of claim 13 , further comprising a third nanostructure transistor including third semiconductor nanostructures, wherein the second gate metal layer is between the third semiconductor nanostructures.

15. The integrated circuit of claim 13 , wherein the inter-sheet filler layer includes silicon.

16. An integrated circuit, comprising:

a first nanostructure transistor including a plurality of first semiconductor nanostructures;

a second nanostructure transistor including a plurality of second semiconductor nanostructures;

a gate dielectric layer surrounding the first and second semiconductor nanostructures;

a first gate metal layer substantially filling a space between the first semiconductor nanostructures;

a second gate metal layer substantially filling a space between the second semiconductor nanostructures, wherein the second gate metal layer has a thickness less than 0.2 nm between the second semiconductor nanostructures; and

a glue layer on the second gate metal layer.

17. The integrated circuit of claim 16 , wherein the second gate metal layer is on the first gate metal layer on sides of the first semiconductor nanostructures.

18. The integrated circuit of claim 16 , wherein the gate dielectric has a variation in thickness less than 0.2 nm on the second semiconductor nanostructures.

19. The integrated circuit of claim 16 , wherein the first and second gate metal layers are different materials.

20. The integrated circuit of claim 16 , further comprising a gate fill material on the glue layer.