Memory semiconductor devices comprising an anti-ferroelectric material
View Patent ↗Semiconductor devices may include a stacked structure including interlayer insulating layers and gate electrodes alternately stacked in a vertical direction, a core region extending in the vertical direction in the stacked structure, a channel layer on a side surface of the core region and facing the gate electrodes and the interlayer insulating layers, a first dielectric layer, a data storage layer and a second dielectric layer, which are between the channel layer and the gate electrodes in order, and an anti-ferroelectric layer including a portion interposed between the first dielectric layer and a first gate electrode of the gate electrodes. The second dielectric layer may contact the channel layer. The anti-ferroelectric layer may be formed of an anti-ferroelectric material having a tetragonal phase.
1. A semiconductor device comprising:
a stacked structure including interlayer insulating layers and gate electrodes alternately stacked in a vertical direction;
a core region extending in the vertical direction in the stacked structure;
a channel layer on a side surface of the core region and facing the gate electrodes and the interlayer insulating layers;
a second dielectric layer, a data storage layer and a first dielectric layer sequentially stacked on the side surface of the channel layer, the second dielectric layer, the data storage layer and the first dielectric layer being between the channel layer and the gate electrodes, and the second dielectric layer being in contact with the channel layer; and
an anti-ferroelectric layer including a portion interposed between the first dielectric layer and a first gate electrode of the gate electrodes,
wherein the anti-ferroelectric layer has a dynamic dielectric constant and comprises an anti-ferroelectric material having a tetragonal phase, and
each of the first and second dielectric layers includes an oxide layer having a dielectric constant lower than a lowest dielectric constant of the anti-ferroelectric layer.
2. The semiconductor device of claim 1 , wherein the anti-ferroelectric material includes a hafnium (Hf)-based oxide or a zirconium (Zr)-based oxide.
3. The semiconductor device of claim 1 , wherein the anti-ferroelectric material includes a Hf-based oxide doped with an impurity.
4. The semiconductor device of claim 3 , wherein the impurity includes Zr, Al, Si and/or La.
5. The semiconductor device of claim 1 , wherein the anti-ferroelectric layer contacts the first dielectric layer and the first gate electrode.
6. The semiconductor device of claim 1 , wherein the anti-ferroelectric material includes a Zr-based oxide doped with an impurity.
7. The semiconductor device of claim 6 , wherein the impurity includes Hf, Al, Si and/or La.
8. The semiconductor device of claim 1 , wherein
the channel layer includes an undoped silicon layer, and
the core region includes a silicon oxide layer or a silicon oxide layer including a void.
9. The semiconductor device of claim 1 , wherein the anti-ferroelectric layer further includes portions respectively extending on an upper surface and a lower surface of the first gate electrode of the gate electrodes.
10. The semiconductor device of claim 1 , wherein the anti-ferroelectric layer further includes portions interposed between the first dielectric layer and the interlayer insulating layers.
11. A semiconductor device comprising:
a stacked structure including interlayer insulating layers and gate electrodes alternately stacked in a vertical direction;
a core region extending in the vertical direction in the stacked structure;
a channel layer on a side surface of the core region and facing the gate electrodes and the interlayer insulating layers;
a second dielectric layer, a data storage layer and a first dielectric layer sequentially stacked on the side surface of the channel layer, the second dielectric layer, the data storage layer and the first dielectric layer being between the channel layer and the gate electrodes, and the second dielectric layer being in contact with the channel layer; and
an anti-ferroelectric layer including a portion between the first dielectric layer and a first gate electrode of the gate electrodes,
wherein the anti-ferroelectric layer comprises an anti-ferroelectric material having a tetragonal phase,
the first gate electrode of the gate electrodes is a portion of a word line of a memory cell,
the anti-ferroelectric material of the anti-ferroelectric layer has a dynamic dielectric constant that varies corresponding to a magnitude of an electric field between the word line and the channel layer,
the first dielectric layer comprises a first dielectric material, and the second dielectric layer comprises a second dielectric material, and
the data storage layer comprises a third dielectric material that is different from the first and second dielectric materials.
12. The semiconductor device of claim 11 , wherein the anti-ferroelectric material is configured to have a first dielectric constant when the magnitude of the electric field between the word line and the channel layer is zero and is configured to have a second dielectric constant during a programming operation of the memory cell, and the second dielectric constant is greater than the first dielectric constant.
13. The semiconductor device of claim 11 , wherein the anti-ferroelectric material is configured to have a first dielectric constant when the magnitude of the electric field between the word line and the channel layer is zero and is configured to have a second dielectric constant during an erasing operation of the memory cell, and the second dielectric constant is greater than the first dielectric constant.
14. The semiconductor device of claim 11 , wherein the anti-ferroelectric material comprises a Hf-based oxide or a Zr-based oxide.
15. A semiconductor device comprising:
a stacked structure including interlayer insulating layers and gate electrodes alternately stacked in a vertical direction;
a core region extending in the vertical direction the stacked structure;
a channel layer on a side surface of the core region and facing the gate electrodes and the interlayer insulating layers;
a second dielectric layer, a data storage layer and a first dielectric layer sequentially stacked on the side surface of the channel layer, the second dielectric layer, the data storage layer and the first dielectric layer being between the channel layer and the gate electrodes, and the second dielectric layer being in contact with the channel layer;
an anti-ferroelectric layer including a portion between the first dielectric layer and a first gate electrode of the gate electrodes,
a pad pattern in contact with the channel layer on the core region;
a contact plug in contact with the pad pattern on the pad pattern; and
a bit line electrically connected to the contact plug on the contact plug,
wherein the anti-ferroelectric layer comprises an anti-ferroelectric material having a tetragonal phase,
the first gate electrode of the gate electrodes is a portion of a word line,
the anti-ferroelectric material of the anti-ferroelectric layer has a dynamic dielectric constant that varies corresponding to a magnitude of an electric field between the word line and the channel layer,
the first dielectric layer comprises a first silicon oxide layer having a first dielectric constant, and the second dielectric layer comprises a second silicon oxide layer having a second dielectric constant, and
the first dielectric constant and the second dielectric constant are lower than a lowest dielectric constant of the anti-ferroelectric layer.
16. The semiconductor device of claim 15 , wherein the anti-ferroelectric material includes a Hf-based oxide or a Zr-based oxide.
17. The semiconductor device of claim 15 , wherein the pad pattern comprises silicon having an N-type conductivity, and
the channel layer facing the word line comprises undoped silicon.
18. The semiconductor device of claim 16 further comprising a lower structure, wherein the lower structure includes:
a semiconductor substrate;
a peripheral circuit on the semiconductor substrate;
a lower insulating layer extending on the peripheral circuit on the semiconductor substrate; and
a lower pattern layer on the lower insulating layer,
wherein the lower pattern layer includes a doped silicon layer.
19. The semiconductor device of claim 18 , further comprising a horizontal connection layer on the lower pattern layer,
wherein the horizontal connection layer includes a lower connection layer and an upper connection layer on the lower connection layer,
the lower connection layer is in contact with the lower pattern layer,
the upper connection layer is in contact with the lower connection layer,
the core region and the channel layer pass through the horizontal connection layer and protrude into the lower pattern layer,
the lower connection layer is in contact with the channel layer, and
the upper connection layer is spaced apart from the channel layer.
20. The semiconductor device of claim 15 , wherein the data storage layer comprises a dielectric material that is different from the first and second silicon oxide layers.