IP Library Granted Patent US 11,742,426
Granted Patent B2
US 11,742,426 · App. 17/316,832 · Granted Aug 29, 2023

Forming crossbar and non-crossbar transistors on the same substrate

Inventors: Indira Seshadri (Niskayuna, NY); Ardasheir Rahman (Schenectady, NY); Ruilong Xie (Niskayuna, NY); Hemanth Jagannathan (Niskayuna, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L29/785H01L21/823821H01L29/6656H01L29/66795
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Quick Facts
Patent No.
US 11,742,426
App. No.
17/316,832
Granted
Aug 29, 2023
Kind
B2
Abstract

A method of forming a transistor structure is provided. The method includes forming on a substrate first and second mandrels for forming two-dimensional (2D) transistor fin elements defining a pitch gap region, depositing and anisotropically etching back the first spacer material to form first and second spacers in and around the first and second mandrels, respectively, conformally depositing and anisotropically etching back second spacer material around the first and second spacers and in the pitch gap region to define space for forming an odd number of one-dimensional (1D) transistor fin elements in the pitch gap region and depositing and anisotropically etching back the first spacer material in the space with enough cycles to fill the space to form a third spacer.

Claims (15)

1. A method of forming a transistor structure, the method comprising:

forming on a substrate first and second mandrels for forming two-dimensional (2D) transistor fin elements defining a pitch gap region;

depositing and anisotropically etching back first spacer material to form a first spacer around the first mandrel and to form a second spacers around the second mandrel;

conformally depositing and anisotropically etching back second spacer material around the first and second spacers and in the pitch gap region to define space for forming an odd number of one-dimensional (1D) transistor fin elements in the pitch gap region; and

cyclically depositing and anisotropically etching back the first spacer material in the space to fill the space to form a third spacer,

wherein the conformally depositing of the second spacer material is executed such that a critical dimension (CD) of the space differs from a corresponding CD of the 2D transistor fin elements.

2. The method according to claim 1 , wherein the substrate comprises a first hard mask and a second hard masks formed of different hard mask materials and the second spacer material differs from the first spacer material.

3. The method according to claim 2 , wherein the second spacer material is a same material as that of the second hard mask.

4. The method according to claim 1 , wherein the conformally depositing of the second spacer material is controlled to arrive at a predefined critical dimension (CD) of the space.

5. The method according to claim 1 further comprising pulling the first and second mandrels and the second spacer material.

6. The method according to claim 5 further comprising:

etching a first hard mask in accordance with a pattern of the first spacer material;

removing the first spacer material;

fin cutting of a remainder of the first hard mask; and

etching the substrate in accordance with the a pattern of the first hard mask.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2021
From: SESHADRI, INDIRA; RAHMAN, ARDASHEIR; XIE, RUILONG; JAGANNATHAN, HEMANTH
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 056197/0334 →
Continuity (1)
Related Publication 20220367700A1 · Nov 17, 2022