Semiconductor device and method

1. A device comprising:

nanostructures on a substrate, the nanostructures comprising a channel region;

a gate dielectric layer wrapping around each of the nanostructures;

a first work function tuning layer on the gate dielectric layer, the first work function tuning layer comprising a first n-type work function metal, aluminum, and carbon, the first n-type work function metal comprising zirconium, hafnium, or niobium;

a glue layer on the first work function tuning layer; and

a fill layer on the glue layer.

2. The device of claim 1 , wherein respective portions of the first work function tuning layer fill areas between the respective portions of the gate dielectric layer.

3. The device of claim 1 , wherein the fill layer does not extend between adjacent nanostructures.

4. The device of claim 1 , wherein the first work function tuning layer has a thickness in a range of 5 Å to 50 Å.

5. A method comprising:

forming a first set of nanostructures on a substrate, the first set of nanostructures comprising a first channel region;

forming a first gate dielectric layer on the first channel region;

forming a first work function tuning layer on the first gate dielectric layer, the first work function tuning layer comprising zirconium aluminum carbide, hafnium aluminum carbide, niobium aluminum carbide, or combinations thereof;

forming a first barrier layer on the first work function tuning layer, the first barrier layer being forming a glue layer on the first barrier layer; and

formed in-situ with the first work function tuning layer;

forming a fill layer on the glue layer.

6. The method of claim 5 further comprising:

forming a second set of nanostructures on the substrate, the second set of nanostructures comprising a second channel region;

forming a second gate dielectric layer on the second channel region;

forming the first work function tuning layer on the second gate dielectric layer;

forming the first barrier layer on the first work function tuning layer on the second gate dielectric layer; and

removing the first barrier layer and the first work function tuning layer from the second gate dielectric layer.

7. The method of claim 6 further comprising:

after removing the first barrier layer and the first work function tuning layer from the second gate dielectric layer, forming a second work function tuning layer on the second gate dielectric layer.

8. The method of claim 7 , wherein the glue layer and the second work function tuning layer are formed at a same time by a same process.

9. The method of claim 7 , wherein the second work function tuning layer is formed on the glue layer.

10. The method of claim 7 further comprising:

forming a second barrier layer on the first gate dielectric layer, the first work function tuning layer being formed on the second barrier layer.

11. The method of claim 7 , wherein the first gate dielectric layer and the second gate dielectric layer are formed at a same time by a same process.

12. The method of claim 5 , wherein respective portions of the first work function tuning layer fill areas between the respective portions of the first gate dielectric layer.

13. The method of claim 5 , wherein the fill layer does not extend between adjacent nanostructures of the first set of nanostructures.

14. The method of claim 5 , wherein the first work function tuning layer has a thickness in a range of 5 Å to 50 Å.

15. A method comprising:

forming a first set of nanostructures and a second set of nanostructures on a substrate, the first set of nanostructures comprising a first channel region and the second set of nanostructures comprising a second channel region;

forming a gate dielectric layer having a first portion and a second portion, the first portion deposited on the first channel region, the second portion deposited on the second channel region;

forming a n-type work function tuning layer on the first portion of the gate dielectric layer, the second portion of the gate dielectric layer, and the n-type work function tuning layer wrapping around each of the first set of nanostructures, the n-type work function tuning layer comprises zirconium aluminum carbide, hafnium aluminum carbide, niobium aluminum carbide, or combinations thereof;

forming a first barrier layer on and in-situ with the n-type work function tuning layer;

removing the first barrier layer and the n-type work function tuning layer from the second portion of the gate dielectric layer;

forming a p-type work function tuning layer on the first barrier layer on the first set of nanostructures and the second portion of the gate dielectric layer; and

forming a fill layer on the p-type work function tuning layer.

16. The method of claim 15 further comprising:

forming a second barrier layer on the first portion of the gate dielectric layer, the n-type work function tuning layer being formed on the second barrier layer.

17. The method of claim 15 , wherein the p-type work function tuning layer on the first barrier layer on the first set of nanostructures acts as a glue layer.

18. The method of claim 15 , wherein respective portions of the n-type work function tuning layer fill areas between the respective first portions of the gate dielectric layer.

19. The method of claim 15 , wherein respective portions of the p-type work function tuning layer fill areas between the respective second portions of the gate dielectric layer.

20. The method of claim 15 , wherein the fill layer does not extend between adjacent nanostructures of the first set of nanostructures.