On-the-fly multi-bit flip flop generation

1. A method, comprising:

selecting at least two flip-flop blocks from a plurality of candidate flip-flop blocks;

identifying a control block from a plurality of candidate control blocks, the control block being identified based on operational specifications of the selected at least two flip-flop blocks, wherein the operational specifications include one or more of a voltage threshold and a time delay; and

generating a multi-bit flip-flop instance based on the selected flip-flop blocks and the identified control block.

2. The method of claim 1 , wherein characteristics of each flip-flop block of the selected flip-flop blocks are independently selectable from one another.

3. The method of claim 2 , wherein the independently selectable characteristics for each of the selected flip-flop blocks include at least one of:

a voltage threshold of one or more transistors of each of the selected flip-flop blocks; or

a time delay for receiving signals from the control block.

4. The method of claim 1 , wherein generating the multi-bit flip-flop instance includes:

placing the selected flip-flop blocks and the control block in a layout; and

routing straight line interconnections between the control block and the selected flip-flop blocks.

5. The method of claim 1 , further comprising accessing a library having definitions of the plurality of candidate flip-flop blocks and the plurality of candidate control blocks, wherein the selection of the selected flip-flop blocks and the identification of the control block is based on the definitions.

6. The method of claim 1 , wherein each of the selected flip-flop blocks and the control block are treated as separate cells in a circuit layout for the generation of the multi-bit flip-flop instance.

7. The method of claim 1 , further comprising fabricating an integrated circuit to include a multi-bit flip-flop based on the multi-bit flip-flop instance.

8. The method of claim 1 , wherein:

the selected two flip-flop blocks are based on a pre-built multi-bit flip-flop instance; and

the control block is based on a pre-built control block included in the pre-built multi-bit flip-flop instance.

9. A system for multi-bit flip-flop architecture generation, comprising:

a memory storing instructions; and

a processor coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:

generate a plurality of candidate flip-flop blocks, each corresponding to a single bit of a multi-bit flip-flop; and

generate a plurality of candidate control blocks, each configured to generate a clock signal and a scan enable signal to drive the plurality of candidate flip-flop blocks, wherein one of the plurality of candidate control blocks and at least two of the plurality of candidate flip-flop blocks are configured to construct a customized multi-bit flip-flop instance, a quantity of the at least two of the plurality of candidate flip-flop blocks being associated with a number of bits of the customized multi-bit flip-flop instance, and wherein the one of the plurality candidate control blocks is associated with at least one of a voltage threshold and a time delay of the at least two of the plurality of candidate flip-flop blocks.

10. The system of claim 9 , wherein each of the plurality of candidate control blocks correspond to sub-circuits used to drive flip-flops of a fixed multi-bit flip-flop.

11. The system of claim 9 , wherein internal connections in the customized multi-bit flip-flop instance are configured for routing after a placement phase of a chip design flow and before auto-routing of global signals.

12. The system of claim 9 , wherein each of the plurality of candidate control blocks is further configured to generate set or reset signals.

13. The system of claim 9 , wherein the plurality of candidate flip-flop blocks represents different transistor drive strengths and transistor types.

14. The system of claim 9 , wherein each of the plurality of candidate flip-flop blocks and the plurality of candidate control blocks is associated with a preconfigured circuit board layout structure, and wherein the preconfigured circuit board layout structure allows for abutment of the at least two of the plurality of candidate flip-flop blocks or the plurality of candidate control blocks.

15. The system of claim 9 , wherein at least one of the plurality of candidate control blocks includes a clock delay block to inject clock signal skew for at least one of the plurality of candidate flip-flop block.

16. The system of claim 9 , wherein at least one of the plurality of candidate control blocks includes an integrated clock gating block configured to selectively disable at least one clock signal for at least one of the plurality of candidate flip-flop blocks.