Methods and apparatus to implement pulse swallowing circuitry in a phase frequency detector

1. A phase frequency detector (PFD) comprising:

a first flip flop having a first output and a first reset input;

a second flip flop having a first data input, a second output, and a second reset input, the second reset input coupled to the first reset input;

a first logic gate having a first logic gate input, a second logic gate input, and a first logic gate output, the first logic gate input coupled to the first output and the second logic gate input coupled to the second output;

a delay cell having a delay cell input and a delay cell output, the delay cell input coupled to the first logic gate output and the delay cell output coupled to the first reset input and the second reset input; and

pulse swallowing circuitry having a circuitry input and a circuitry output, the circuitry input coupled to the second output and the circuitry output coupled to the first data input, the pulse swallowing circuitry further comprising:

a third flip-flop having a third reset input and a third output;

a second logic gate having a third logic gate input, a fourth logic gate input, and a second logic gate output, the third logic gate input coupled to the second output, the fourth logic gate input coupled to the third output, and the second logic gate output coupled to the first data input; and

a one-shot circuit having a one-shot input and a one-shot output, the one-shot input coupled to the second output and the one-shot output coupled to the third reset input.

2. The PFD of claim 1 ,

wherein the first flip flop further comprises a first clock input and the second flip flop further comprises a second clock input, the first clock input is configured to receive a reference clock signal and the second clock input is configured to receive a modulated clock signal.

3. The PFD of claim 2 , wherein the modulated clock signal has a first frequency that is N times that of a second frequency corresponding to reference clock signal.

4. The PFD of claim 1 , wherein the third flip flop has a clock input configured to receive a modulated clock signal.

5. The PFD of claim 4 , wherein the first logic gate comprises a logic AND gate and the second logic gate comprises a logic OR gate.

6. A phase frequency detector (PFD) comprising:

a first flip flop having a first output and a first reset input;

a second flip flop having a first data input, a second output, and a second reset input the second reset input coupled to the first reset input,

a logic gate having a first logic gate input, a second logic gate input, and first logic gate output, the first logic gate input coupled to the first output and the second logic gate input coupled to the second output,

a delay cell having a delay cell input and a delay cell output, the delay cell input coupled to the first logic gate output and the delay cell output coupled to the first reset input and the second reset input; and

pulse swallowing circuitry having a circuitry input and a circuitry output, the circuitry input coupled to the second output and the circuitry output coupled to the first data input,

wherein the first flip flop further includes a first clock input, the second flip flop further includes a second clock input, and the pulse swallowing circuitry further comprises:

a third flip flop having a third clock input, the third clock input and the second clock input configured to receive a modulated clock signal and the first clock input configured to receive a reference clock input, the modulated clock signal having a first frequency that is N times that of a second frequency corresponding to reference clock signal.

7. A system comprising:

a phase frequency detector having a first input, a second input, a third input, a first output, and a second output, the second input configured to receive a reference clock signal, and the third input configured to receive a control signal indicative of a ratio between the reference clock signal and the fifth output of the voltage controlled oscillator;

a charge pump having a third output, the charge pump coupled to the first and second outputs;

a loop filter having a fourth output, the loop filter coupled to the third output; and

a voltage controlled oscillator coupled to the fourth output and having a fifth output directly coupled to the first input of the phase frequency detector.

8. The system of claim 7 , wherein the phase frequency detector further comprises:

a first flip flop having a first clock input, a first reset input, and a first data output, the first clock input configured to receive a reference clock signal and the first data output coupled to the charge pump;

a second flip flop having a first data input, a second clock input, a second reset input, and a second data output, the second clock input coupled to the fifth output, the second reset input coupled to the first reset input, and the second data output coupled to the charge pump;

a logic gate having a first logic gate input, a second logic gate input, and a first logic gate output, the first logic gate input coupled to the first data output and the second logic gate input coupled to the second data output;

a delay cell having a delay cell input and a delay cell output, the delay cell input coupled to the first logic gate output and the delay cell output coupled to the first reset input and the second reset input; and

pulse swallowing circuitry having a circuit input and a circuit output, the circuit input coupled to the second data output and the circuit output coupled to the first data input.

9. The system of claim 7 , wherein the phase frequency detector further comprises pulse swallowing circuitry coupled to the fifth output.

10. The system of claim 7 , wherein the first output is configured to transmit an UP signal indicative of a reference clock signal and the second output is configured to transmit a DOWN signal indicative of a modulated signal.

11. The system of claim 10 , wherein the fifth output of the voltage controlled oscillator is configured to transmit the modulated signal, wherein the modulated signal includes a first frequency that is N times a second frequency corresponding to the reference clock signal.

12. The system of claim 7 , wherein the phase frequency detector further comprises:

a first flip flop having a first clock input, a first reset input, and a first data output, the first clock input configured to receive a reference clock signal and the first data output coupled to the charge pump;

a second flip flop having a first data input, a second clock input, a second reset input, and a second data output, the second clock input coupled to the fifth output, the second reset input coupled to the first reset input, and the second data output coupled to the charge pump;

a second logic gate having a first logic gate input, a second logic gate input, and a first logic gate output, the first logic gate input coupled to the first data output and the second logic gate input coupled to the second data output;

a delay cell having a delay cell input and a delay cell output, the delay cell input coupled to the first logic gate output and the delay cell output coupled to the first reset input and the second reset input; and

pulse swallowing circuitry comprising:

a third flip flop having a third clock input, a third reset input, and a third data output, the third clock input configured to be coupled to the fifth output;

a second logic gate having a third logic gate input, a fourth logic gate input, and a second logic gate output, the third logic gate input coupled to the second data output, the fourth logic gate input coupled to the third data output, and the second logic gate output coupled to the first data input; and

a one-shot circuit having a one-shot input and a one-shot output, the one-shot input coupled to the second data output and the one-shot output coupled to the third reset input.

13. A method comprising:

latching a low voltage at a first flip flop output responsive to a first rising edge on a first clock signal;

latching a high voltage at a second flip flop output responsive to the first rising edge on the first clock signal;

inputting a high voltage at a first flip flop input responsive to latching the high voltage at the second flip flop output; and

latching the high voltage on the first flip flop input at the first flip flop output responsive to a second rising edge on the first clock signal, the second rising edge occurring at a time after the first rising edge.

14. The method of claim 13 , further including triggering a one-shot circuit responsive to the high voltage at the first flip flop output responsive to the second rising edge of the first clock signal.

15. The method of claim 13 , further including:

triggering a one-shot circuit responsive to the high voltage at the first flip flop output responsive to the second rising edge of the first clock signal;

resetting the second flip flop output responsive to triggering the one-shot circuit, the one-shot circuit to input a pulse at a second flip flop reset input; and

providing a low voltage to a logic gate responsive to resetting the second flip flop output.

16. The method of claim 13 , further including:

providing the high voltage on the first flip flop output to a logic AND gate responsive to the second rising edge on the first clock signal;

latching a high voltage at a third flip flop output responsive to a first rising edge on a second clock signal, the second clock signal out of phase with the first clock signal;

providing the high voltage on the third flip flop output to the logic AND gate; and

outputting a reset signal to a first flip flop reset input and a third flip flop reset input responsive to the high voltage from the first flip flop output and the high voltage from the third flip flop output, the reset signal to reset the first flip flop output and the third flip flop output.

17. The method of claim 13 , further including:

triggering a one-shot circuit responsive to the high voltage at the first flip flop output responsive to the second rising edge of the first clock signal;

resetting the second flip flop output responsive to triggering the one-shot circuit, the one-shot circuit to input a pulse at a second flip flop reset input;

providing a low voltage to a first logic gate responsive to resetting the second flip flop output;

providing the high voltage on the first flip flop output to a logic AND gate responsive to the second rising edge on the first clock signal;

latching a high voltage at a third flip flop output responsive to a first rising edge on a second clock signal, the second clock signal out of phase with the first clock signal;

providing the high voltage on the third flip flop output to the logic AND gate;

outputting a reset signal to a first flip flop reset input and a third flip flop reset input responsive to the high voltage from the first flip flop output and the high voltage from the third flip flop output, the reset signal to reset the first flip flop output and the third flip flop output;

inputting a low voltage at the first flip flop input responsive to latching the first flip flop output resetting; and

latching a low voltage at the first flip flop output responsive to a third rising edge on the first clock signal, the third rising edge occurring at a time after the second rising edge.

18. The method of claim 13 , further including:

determining a ratio N between the first clock signal and a second clock signal; and

sampling the first clock signal at every Nth edge of the first clock signal, wherein every Nth edge corresponds to the ratio N.