High performance persistent memory

1. A buffer device of a memory system, the buffer device comprising:

a first interface to couple to one or more memory devices of a first memory type;

a second interface to couple to one or more memory device of a second memory type, wherein the first memory type is volatile memory and the second memory type is non-volatile memory; and

a control element coupled to the first interface and the second interface, wherein the control element is to:

capture an initial base image of data in the one or more memory devices of the first memory type;

store the initial base image in the one or more memory devices of the second memory type;

track incremental updates to the data in the one or more memory devices of the first memory type; and

transfer the incremental updates to the one or more memory devices of the second memory type;

determine whether a system failure has occurred; and

when the system failure has occurred, restore the initial base image and any of the incremental updates into the one or more memory devices of the first memory type.

2. The buffer device of claim 1 , wherein the control element, to track the incremental updates, is to:

determine the incremental updates to the data stored in the one or more memory devices of the first memory type;

create a journal of the incremental updates; and

store the journal of the incremental updates in the one or more memory devices of the first memory type.

3. The buffer device of claim 1 , wherein the control element, to track the incremental updates, is to:

determine the incremental updates to the data stored in the one or more memory devices of the first memory type;

create a journal of the incremental updates; and

store the journal of the incremental updates in one or more memory devices of a third memory type, wherein the third memory type is non-volatile memory that has higher speeds than the second memory type.

4. The buffer device of claim 1 , wherein the control element, to track the incremental updates, is to store a scorecard in the one or more memory devices of the first memory type, the scorecard indicating, for storage blocks of the one or more memory devices of the first memory type, whether the current contents of each storage block have been saved in the one or more memory devices of the second memory type or not saved in the one or more memory devices of the second memory type.

5. The buffer device of claim 4 , wherein the control element is further to store an aging indicator in the scorecard for each storage block for which the current contents have not been saved in the one or more memory devices of the second memory type, the control element to use the aging indicator to select an order to save blocks from the one or more memory devices of the first memory type to the one or more memory devices of the second memory type.

6. The buffer device of claim 4 , wherein the control element is further to store a first address in the scorecard for each storage block, the address indicating, when the current contents of a given storage block have been saved in the one or more memory devices of the second memory type, a location in the one or more memory devices of the second memory type containing a valid copy of the given storage block.

7. The buffer device of claim 6 , wherein the control element is further to store in the one or more memory devices of the second memory type, for each storage block that is valid in the one or more memory devices of the second memory type, an address corresponding to an entry in the scorecard for that storage block.

8. The buffer device of claim 7 , wherein the control element is to save updated storage blocks from the one or more memory devices of the first memory type to the one or more memory devices of the second memory type in an address sequence progression that is independent of the locations of the updated storage blocks in the one or more memory devices of the first memory type.

9. The buffer device of claim 8 , wherein the control element is to run a consolidation routine in the same address sequence progression, using the scorecard, to reclaim storage blocks in the one or more memory devices of the second memory type that contain stale data.

10. The buffer device of claim 1 , wherein the second memory type has at least one of a lower access speed, lower endurance, or a lower bit cost than the first memory type.

11. The buffer device of claim 1 , wherein the first memory type is a dynamic random access memory (DRAM) device, wherein the second memory type is at least one of a NOR flash device, a static RAM (SRAM) device, a pseudo static RAM device, an erasable programmable read only memory (EPROM) device, or an electrically erasable programmable ROM (EEPROM) device.

12. The buffer device of claim 1 , wherein the first memory type is a dynamic random access memory (DRAM) device, wherein the second memory type is at least one of a resistive RAM (ReRAM) device, a magnetoresistive RAM (MRAM) device, a phase-change memory device, or a racetrack memory device.

13. The buffer device of claim 1 , wherein the control element is to store a journal of the incremental updates in a memory device of a third memory type, wherein the third memory type is higher speed than the second memory type.

14. The buffer device of claim 1 , wherein the control element is to store a journal of the incremental updates in a memory device of a third memory type, wherein the third memory type is non-volatile memory, wherein the second memory type has at least one of a lower access speed, lower endurance, or a lower bit cost than the third memory type, and wherein the third memory type has at least one of a lower access speed, lower endurance, or a lower bit cost than the first memory type.

15. The buffer device of claim 14 , wherein the first memory type is a dynamic random access memory (DRAM) device, wherein the second memory type is at least one of a NAND flash device, a NOR flash device, a static RAM (SRAM) device, a pseudo static RAM device, an erasable programmable read only memory (EPROM) device, or an electrically erasable programmable ROM (EEPROM) device, and wherein the third memory type is at least one of resistive random access memory (ReRAM) device, a magnetoresistive RAM (MRAM) device, a phase-change memory device, or a racetrack memory device.

16. An integrated circuit comprising:

a first interface to couple to one or more memory devices of a first memory type;

a second interface to couple to one or more memory device of a second memory type, wherein the first memory type is volatile memory and the second memory type is non-volatile memory; and

a digital circuit coupled to the first interface and the second interface, wherein the digital circuit is to:

capture an initial base image of data in the one or more memory devices of the first memory type;

store the initial base image in the one or more memory devices of the second memory type;

track incremental updates to the data in the one or more memory devices of the first memory type; and

transfer the incremental updates to the one or more memory devices of the second memory type;

determine whether a system failure has occurred; and

when the system failure has occurred, restore the initial base image and any of the incremental updates into the one or more memory devices of the first memory type.

17. The integrated circuit of claim 16 , wherein the digital circuit, to track the incremental updates, is to:

determine the incremental updates to the data stored in the one or more memory devices of the first memory type;

create a journal of the incremental updates; and

store the journal of the incremental updates in the one or more memory devices of the first memory type.

18. The integrated circuit of claim 16 , wherein the digital circuit, to track the incremental updates, is to:

determine the incremental updates to the data stored in the one or more memory devices of the first memory type;

create a journal of the incremental updates; and

store the journal of the incremental updates in one or more memory devices of a third memory type, wherein the third memory type is non-volatile memory that has higher speeds than the second memory type.

19. A memory system comprising:

a buffer device access one or more memory devices of a first memory type; and

an integrated circuit coupled to the buffer device and one or more memory devices of a second memory type, wherein the first memory type is volatile memory and the second memory type is non-volatile memory, and wherein the integrated circuit is to:

receive, from the buffer device, an initial base image of data in the one or more memory devices of the first memory type;

store the initial base image in the one or more memory devices of the second memory type;

track incremental updates to the data in the one or more memory devices of the first memory type; and

transfer the incremental updates to the one or more memory devices of the second memory type;

determine whether a system failure has occurred; and

when the system failure has occurred, restore the initial base image and any of the incremental updates into the one or more memory devices of the first memory type.

20. The memory system of claim 19 , wherein the integrated circuit, to track the incremental updates, is to:

determine the incremental updates to the data stored in the one or more memory devices of the first memory type; and

create a journal of the incremental updates, wherein the journal is stored in the one or more memory devices of the first memory type or updates in one or more memory devices of a third memory type, wherein the third memory type is non-volatile memory that has higher speeds than the second memory type.