Circuit devices with gate seals
Various examples of a circuit device that includes gate stacks and gate seals are disclosed herein. In an example, a substrate is received that has a fin extending from the substrate. A placeholder gate is formed on the fin, and first and second gate seals are formed on sides of the placeholder gate. The placeholder gate is selectively removed to form a recess between side surfaces of the first gate seal and the second gate seal. A functional gate is formed within the recess and between the side surfaces of the first gate seal and the second gate seal.
1. A semiconductor structure, comprising:
a semiconductor fin protruding from a substrate;
an interfacial layer disposed over a channel region of the semiconductor fin;
a metal gate stack disposed over the interfacial layer;
a gate seal disposed along a sidewall of the metal gate stack and in physical contact with the interfacial layer; and
a gate spacer disposed along the gate seal, wherein a bottom portion of the gate spacer extends along to physically contact a top surface of the interfacial layer.
2. The semiconductor structure of claim 1 , wherein the gate spacer includes a first spacer layer disposed along the gate seal, a second spacer layer disposed along the first spacer layer, and a third spacer layer disposed along the second spacer layer.
3. The semiconductor structure of claim 2 , wherein the gate seal differs from the first spacer layer in composition.
4. The semiconductor structure of claim 2 , wherein a bottom portion of the first spacer layer extends along and is in direct contact with the interfacial layer.
5. The semiconductor structure of claim 1 , wherein the gate seal includes polysilicon oxide.
6. The semiconductor structure of claim 5 , wherein the interfacial layer includes polysilicon oxide.
7. The semiconductor structure of claim 1 , wherein the metal gate stack includes a gate dielectric layer disposed along the gate seal, a work function layer disposed over the gate dielectric layer, and an electrode fill disposed over the work function layer.
8. The semiconductor structure of claim 7 , further comprising a dielectric capping layer spanning across a top portion of the metal gate stack, wherein a sidewall of the dielectric capping layer is defined by the gate seal.
9. A semiconductor structure, comprising:
a semiconductor substrate;
an isolation feature disposed on the semiconductor substrate;
a fin extending vertically from a top surface of the semiconductor substrate and through the isolation feature such that a top surface of the fin is higher than a top surface of the isolation feature;
source/drain (S/D) features disposed in the fin;
a first oxide layer disposed on the fin and extends to contact the S/D features;
a gate structure disposed over the first oxide layer;
a second oxide layer disposed along a sidewall of the gate structure to directly contact the first oxide layer; and
a gate spacer disposed along the second oxide layer, wherein a horizontal portion of the gate spacer directly contacts the first oxide layer.
10. The semiconductor structure of claim 9 , wherein the first oxide layer and the second oxide layer both include polysilicon oxide.
11. The semiconductor structure of claim 9 , wherein the gate structure includes a gate dielectric layer, wherein a horizontal portion of the gate dielectric layer directly contacts the first oxide layer, and wherein a vertical portion of the gate dielectric layer directly contacts the second oxide layer.
12. The semiconductor structure of claim 9 , wherein the gate spacer includes a first spacer layer disposed along the second oxide layer, a second spacer layer disposed along the first spacer layer, and a third spacer layer disposed along the second spacer layer.
13. The semiconductor structure of claim 12 , wherein a horizontal portion of the first spacer layer directly contacts the first oxide layer.
14. The semiconductor structure of claim 12 , wherein the second oxide layer is free of contact with the second spacer layer and the third spacer layer.
15. The semiconductor structure of claim 12 , wherein the second oxide layer includes polysilicon oxide and the first spacer layer includes silicon oxycarbonitride.
16. A semiconductor structure, comprising:
a substrate;
an isolation feature over the substrate;
a semiconductor fin protruding from a top surface of the substrate and extend through the isolation feature such that a top surface of the semiconductor fin rises over a top surface of the isolation feature;
an interfacial layer disposed over a channel region of the semiconductor fin;
a gate structure disposed over the interfacial layer, wherein the gate structure includes a gate dielectric layer and a gate electrode over the gate dielectric layer;
a dielectric gate seal disposed on a sidewall of the gate structure; and
a gate spacer disposed on the dielectric gate seal, wherein the dielectric gate seal defines a sidewall of the gate dielectric layer and a sidewall of the gate spacer, respectively, and wherein a bottom surface of the gate spacer laterally extends along and is in direct contact with a top surface of the interfacial layer.
17. The semiconductor structure of claim 16 , further comprising source/drain (S/D) features over the semiconductor fin and adjacent to the gate structure, wherein the interfacial layer extends to contact the S/D features.
18. The semiconductor structure of claim 16 , further comprising a dielectric capping feature disposed over the gate structure, wherein the dielectric capping feature laterally extends between sidewalls of the gate structure to directly contact the dielectric gate seal.
19. The semiconductor structure of claim 16 , wherein the gate spacer and the dielectric gate seal differ in composition.
20. The semiconductor structure of claim 19 , wherein the dielectric gate seal includes polysilicon oxide and the gate spacer includes silicon oxycarbonitride.