High gain resonant amplifier for resistive output impedance

1. An apparatus comprising:

a resonant amplifier circuit, wherein the resonant amplifier circuit comprises:

a first inductor having a first inductive input and a first inductive output;

a second inductor having a second inductive input and a second inductive output;

a first switch coupled, via a first terminal of the first switch, to the first inductive output; and

a second switch coupled, via a second terminal of the second switch, to the second inductive output, wherein the first switch and the second switch are driven out of phase based at least in part on a clock signal,

wherein the first inductor is configured to be resonant with a first capacitance coupled across the first terminal of the first switch and a second terminal of the first switch,

wherein the second inductor is configured to be resonant with a second capacitance coupled across a first terminal of the second switch and the second terminal of the second switch,

wherein the first inductive output of the first inductor is coupled to the first terminal of the first switch and a second terminal of the first capacitance, and

wherein the second inductive output of the second inductor is coupled to the second terminal of the second switch and a second terminal of the second capacitance;

an impedance matching circuit configured to enable an impedance match to a load coupled to an output of the apparatus; and

a direct current filtering circuit configured to at least enable blocking at least a portion of direct current from reaching the load coupled to the output of the apparatus.

2. The apparatus of claim 1 , wherein the first inductive input first and the second inductive input are coupled such that the first inductive input first and the second inductive input share a common input.

3. The apparatus of claim 1 , wherein the impedance matching circuit further comprises a first matching inductor, a second matching inductor, and a matching capacitor.

4. The method of claim 3 , wherein the first inductive output is further coupled to the first matching inductor, wherein the second inductive output is further coupled to the second matching inductor, and wherein the matching capacitor is coupled to the first matching inductor and the second matching inductor.

5. The apparatus of claim 1 , wherein the direct current filtering circuit further comprises a first capacitor and a second capacitor.

6. The apparatus of claim 5 , wherein the first capacitor and the second capacitor are each coupled to the load coupled to the output of the apparatus.

7. The apparatus of claim 4 , wherein the direct current filtering circuit is coupled between the resonant amplifier circuit and the load coupled to the output of the apparatus.

8. The apparatus of claim 1 , wherein the output of the apparatus provides a voltage output to the load coupled to the output of the apparatus, wherein the voltage output is processed by at least the impedance matching circuit and the direct current filtering circuit before being provided to the load.

9. The apparatus of claim 1 further comprising the load, wherein the load is an impedance load.

10. The apparatus of claim 1 , wherein the resonant amplifier circuit comprises, or is comprised in, a radio frequency resonant amplifier circuit.

11. The apparatus of claim 1 , further comprising a plurality of resonant amplifier circuits, such that an output of the apparatus generates a plasma at the load coupled to the output of the apparatus.

12. The apparatus of claim 1 , wherein the resonant amplifier circuit operates within a frequency range of 20 kHz to 300 GHz.

13. The apparatus of claim 1 , wherein the first inductor comprises at least a one inductor.

14. The apparatus of claim 1 , wherein the second inductor comprises at least one inductor.

15. The apparatus of claim 1 , wherein the first switch comprises a plurality of first switches.

16. The apparatus of claim 14 , wherein the plurality of first switches share a common clock configured to turn the plurality of first switches on and/or off at a same time.

17. The apparatus of claim 1 , wherein the second switch comprises a plurality of second switches.

18. The apparatus of claim 1 , wherein the first switch and the second switch are driven out of phase by 180 degrees based on the clock signal provided to a third terminal of the first switch and a third terminal of the second switch.

19. The apparatus of claim 1 , wherein the clock signal having a duty cycle of 50%.

20. The apparatus of claim 1 , wherein the first switch comprises a plurality of first switches, and wherein the second switch comprises a plurality of second switches, and wherein one of the switches of the plurality of first switches and another switch in the plurality of second switches share an interval, wherein during a first portion of the interval the one of the switches of the plurality of first switches is gated to turn on and off and then during a second portion of the interval the other switch in the plurality of second switches is gated to turn on and off.

21. The apparatus of claim 1 , wherein the first switch comprises a field-effect transistor, a high-electron-mobility transistor (HEMT), a gallium nitride (GaN) HEMT, a gallium arsenide (GaAs) HEMT, a bipolar junction transistor (BJT), an insulated-gate bipolar transistor (IGBT), a junction gate field-effect transistor, a thyristor, a metal-oxide-semiconductor field-effect transistor (MOSFET), a silicon carbide (SiC) (MOSFET), a silicon (Si) (MOSFET), a diode, and/or a silicon-controlled rectifier, and wherein the second switch comprises a field-effect transistor, a high-electron-mobility transistor (HEMT), a gallium nitride (GaN) HEMT, a gallium arsenide (GaAs) HEMT, a bipolar junction transistor (BJT), an insulated-gate bipolar transistor (IGBT), a junction gate field-effect transistor, a thyristor, a metal-oxide-semiconductor field-effect transistor (MOSFET), a silicon carbide (SiC) (MOSFET), a silicon (Si) (MOSFET), a diode, and/or a silicon-controlled rectifier.