Power optimized timer module for processors
A timer intellectual property (IP) block that automatically determines an interval on which a processor circuitry is to be woken up to service periodic events, when it is given details about the requirements for those events (e.g., approximately how often they must occur, if it's important that they not happen too frequently or too infrequently, if the total number of events over a long average is important, etc.). For each periodic event that firmware must handle, the IP provides an Application Programming Interface (API) to register details of that event. The firmware configures all the events that it requires during system configuration, although it is possible to add, remove or modify individual events at runtime. At runtime, the optimized timer IP will interrupt the processor circuitry whenever one or more events need to be handled, based on a batching algorithm.
1. An apparatus comprising:
a processor circuitry to execute one or more instructions, wherein the processor circuitry is to configure a plurality of parameters for each timer event, and provide the plurality of parameters to an application programming interface; and
a timer circuitry to receive the plurality of parameters that are configured by the processor circuitry, and to batch a plurality of timer events according to the plurality of parameters, wherein the plurality of parameters comprises a long-term quantity requirement for each timer event of the plurality of timer events.
2. The apparatus of claim 1 , wherein the plurality of parameters comprises an approximate event period for each timer event of the plurality of timer events.
3. The apparatus of claim 1 , wherein the plurality of parameters comprises an enable parameter for each timer event of the plurality of timer events.
4. The apparatus of claim 1 , wherein the timer circuitry is to interrupt the processor circuitry at runtime at periodic times.
5. The apparatus of claim 4 , wherein the periodic times are based on a most frequent event from among the plurality of timer events.
6. The apparatus of claim 1 , wherein the timer circuitry is to set an interrupt field as pending when an approximate event period will expire before a next wake period for the processor circuitry.
7. The apparatus of claim 1 , wherein the timer circuitry is to set an interrupt field as pending when an event period for a timer event has already expired.
8. An apparatus comprising:
a processor circuitry to execute one or more instructions, wherein the processor circuitry is to configure a plurality of parameters for each timer event, and provide the plurality of parameters to an application programming interface; and
a timer circuitry to receive the plurality of parameters that are configured by the processor circuitry, and to batch a plurality of timer events according to the plurality of parameters, wherein the timer circuitry is to set an interrupt field as pending when a long-term average shows that more events are desired for a given time period.
9. The apparatus of claim 8 , wherein the plurality of parameters comprises an arrival preference for each timer event of the plurality of timer events.
10. The apparatus of claim 8 , wherein the timer circuitry determines a minimum wake period from among the plurality of timer events for which the plurality of parameters is configured.
11. The apparatus of claim 8 , wherein the application programming interface includes an event registration interface to register the plurality of parameters for each timer event.
12. An apparatus comprising:
a processor circuitry to execute one or more instructions, wherein the processor circuitry is to configure a plurality of parameters for each timer event, and provide the plurality of parameters to an application programming interface; and
a timer circuitry to receive the plurality of parameters that are configured by the processor circuitry, and to batch a plurality of timer events at regular time intervals according to the plurality of parameters and a minimum wake period for a number of timer events, wherein the timer circuitry is to set an interrupt field as pending when a long-term average shows that more events are desired for a given time period.
13. The apparatus of claim 12 , wherein the timer circuitry determines the minimum wake period from among the plurality of timer events for which the plurality of parameters is configured.
14. The apparatus of claim 12 , wherein the plurality of parameters comprises:
an approximate event period for each timer event of the plurality of timer events;
an arrival preference for each timer event of the plurality of timer events;
a long-term quantity requirement for each timer event of the plurality of timer events; and
an enable parameter for each timer event of the plurality of timer events.
15. The apparatus of claim 12 , wherein the timer circuitry is to set an interrupt field as pending when an approximate event period will expire before a next wake period for the processor circuitry.
16. The apparatus of claim 12 , wherein the timer circuitry is to set an interrupt field as pending when an event period for a timer event has already expired.