Analog content-address memory and operation method thereof
An analog CAM and an operation method thereof are provided. The analog CAM includes a matching line, an analog CAM cell and a sense amplifier. Each of the at least one analog CAM includes a first floating gate device having a N type channel and a second floating gate device having a P type channel. A match range is set through programming the first floating gate device and the second floating gate device. The sense amplifier is connected to the matching line. If an inputting signal is within the match range, a voltage of the matching line is pulled down to be equal to or lower than a predetermined level. The sense amplifier outputs a match result if the voltage of the matching line is pulled down to a predetermined level.
1. An analog content-address memory (analog CAM), comprising:
at least one matching line;
at least one analog CAM cell, each of which includes:
a first floating gate device having a N type channel, wherein the first floating gate device is connected to the matching line; and
a second floating gate device having a P type channel, wherein the first floating gate device and the second floating gate device are connected in series, a match range is set through programming the first floating gate device and the second floating gate device, and the first floating gate device and the second floating gate device of the analog CAM cell are configured to receive an inputting signal; and
at least one sense amplifier, connected to the matching line, wherein if the inputting signal is within the match range, a voltage of the matching line is pulled down to be equal to or lower than a predetermined level and the sense amplifier outputs a match result.
2. The analog CAM according to claim 1 , wherein the voltage of the matching line is kept if the inputting signal is not within the match range.
3. The analog CAM according to claim 1 , wherein the first floating gate device is a NMOS, and the second floating gate device is a PMOS.
4. The analog CAM according to claim 1 , wherein a threshold voltage of the first floating gate device is lower than a threshold voltage of the second floating gate device.
5. The analog CAM according to claim 1 , wherein a lower bound of the match range is set through the first floating gate device, and an upper bound of the match range is set through the second floating gate device.
6. The analog CAM according to claim 1 , wherein the first floating gate device and the second floating gate device simultaneously receive the inputting signal.
7. The analog CAM according to claim 1 , wherein the first floating gate device is a N channel Thyristor RAM, and the second floating gate device is a P channel Thyristor RAM.
8. The analog CAM according to claim 1 , wherein the first floating gate device is a N channel gate control thyristor, and the second floating gate device is a P channel gate control thyristor.
9. An analog content-address memory (analog CAM), comprising:
at least one matching line;
at least one analog CAM cell, each of which includes:
a first floating gate device having a N type channel, wherein the first floating gate device is connected to the matching line; and
a second floating gate device having a P type channel, wherein the first floating gate device and the second floating gate device are connected in parallel, a match range is set through programming the first floating gate device and the second floating gate device, and the first floating gate device and the second floating gate device are configured to receive an inputting signal; and
at least one sense amplifier, connected to the matching line, wherein, if the inputting signal is within the match range, a voltage of the matching line is kept at an original level and the sense amplifier outputs a match result.
10. The analog CAM according to claim 9 , wherein the voltage of the matching line is pulled down if the inputting signal is not within the match range.
11. The analog CAM according to claim 9 , wherein the first floating gate device is a NMOS, and the second floating gate device is a PMOS.
12. The analog CAM according to claim 9 , wherein a threshold voltage of the first floating gate device is higher than a threshold voltage of the second floating gate device.
13. The analog CAM according to claim 9 , wherein a lower bound of the match range is set through the second floating gate device, and an upper bound of the match range is set through the first floating gate device.
14. The analog CAM according to claim 9 , wherein the first floating gate device and the second floating gate device simultaneously receive the inputting signal.
15. The analog CAM according to claim 9 , wherein the first floating gate device is a N channel Thyristor RAM, and the second floating gate device is a P channel Thyristor RAM.
16. The analog CAM according to claim 9 , wherein the first floating gate device is a N channel gate control thyristor, and the second floating gate device is a P channel gate control thyristor.
17. An operation method of an analog content-address memory (analog CAM), comprising:
programing a first floating gate device having a N type channel; and
programing a second floating gate device having a P type channel, wherein the second floating gate device is connected to the first floating gate device in series or in parallel, a match range is set after programming the first floating gate device and the second floating gate device.
18. The operation method of the analog CAM according to claim 17 , wherein the first floating gate device and the second floating gate device are programmed by Fowler— Nordheim (FN) tunneling or Channel Hot Electron (CHE) programming.
19. The operation method of the analog CAM according to claim 17 , further comprising:
inputting an inputting signal into the first floating gate device and the second floating gate device; and
outputting a match result or a mismatch result according to a voltage of a matching line connected to the first floating gate device and the second floating gate device.
20. The operation method of the analog CAM according to claim 17 , wherein the inputting signal is simultaneously inputted into the first floating gate device and the second floating gate device.