IP Library › Granted Patent US 12,185,009
Granted Patent B2
US 12,185,009 · App. 17/326,242 · Granted Dec 31, 2024

Image sensor, method of controlling image sensor, and electronic device

Inventors: Atsumi Niwa (Kanagawa, JP); Tomonori Yamashita (Kanagawa, JP); Takashi Moue (Kanagawa, JP); Yosuke Ueno (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H04N25/772H03K5/2481H03M1/34H04N25/75
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Quick Facts
Patent No.
US 12,185,009
App. No.
17/326,242
Granted
Dec 31, 2024
Kind
B2
Abstract

Provided is an image sensor including: a pixel section configured to include a plurality of pixels arranged therein; and an AD conversion unit configured to perform analog-to-digital (AD) conversion on a pixel signal on the basis of a result of comparison between a first voltage of a signal, which is obtained by adding, via capacitances, the pixel signal of the pixel and a reference signal that linearly changes in a direction opposite to the pixel signal, with a second voltage serving as a reference.

Claims (52)

1. A light detecting device comprising:

a pixel configured to generate a pixel signal; and

a comparator comprising:

a first capacitor configured to receive the pixel signal;

a second capacitor configured to receive a reference signal;

a first node coupled to the first capacitor and the second capacitor wherein the first node is a single-type amplifier;

a first transistor having a gate coupled to the first node;

a second transistor disposed between a first line supplied with a first voltage and the first transistor;

a third capacitor coupled to a gate of the second transistor and the first line; and

a third transistor disposed between the first transistor and the second transistor,

a fourth transistor coupled to the third transistor and a switch coupled between a gate and a drain of the fourth transistor;

wherein the first transistor is coupled between the second transistor and a second line supplied with a second voltage different from the first voltage,

wherein a polarity of the first transistor is opposite to a polarity of the second transistor,

wherein a first output signal is configured to output from a second node between the first transistor and the second transistor,

wherein a gate of the second transistor is configured to receive a bias voltage from an external of the comparator.

2. The light detecting device of claim 1 , wherein the bias voltage received by the second transistor is different from the first and second voltage.

3. The light detecting device of claim 1 , wherein the gate of the second transistor is configured to receive the bias voltage via a switch.

4. The light detecting device of claim 1 , wherein a capacitor is coupled to the gate of the second transistor and the first line.

5. The light detecting device of claim 1 , wherein the first capacitor and the second capacitor are variable.

6. The light detecting device of claim 1 , wherein the third transistor is serially coupled to the first transistor and the second transistor.

7. The light detecting device of claim 6 , wherein the gate of the third transistor is configured to receive a via voltage.

8. A light detecting device comprising:

a pixel configured to generate a pixel signal; and

a comparator comprising:

a first capacitor configured to receive the pixel signal;

a second capacitor configured to receive a reference signal;

a first node coupled to the first capacitor and the second capacitor;

a first transistor having a gate coupled to the first node; and

a second transistor disposed between a first line supplied with a first voltage and the first transistor,

wherein the first transistor is coupled between the second transistor and a second line supplied with a second voltage different from the first voltage,

wherein a polarity of the first transistor is opposite to a polarity of the second transistor,

wherein a gate of the second transistor is configured to receive a bias voltage,

wherein a first output signal is configured to output from a second node between the first transistor and the second transistor,

wherein the comparator comprises a third transistor coupled to a third line supplied with a third voltage, and a gate of the third transistor is configured to receive the first output signal, and

wherein the third voltage is equal to the second voltage.

9. The light detecting device of claim 8 , wherein the third voltage is equal to the first voltage.

10. A light detecting device comprising:

a pixel configured to generate a pixel signal; and

a comparator comprising:

a first capacitor configured to receive the pixel signal;

a second capacitor configured to receive a reference signal;

a first node coupled to the first capacitor and the second capacitor;

a first transistor having a gate coupled to the first node; and

a second transistor disposed between a first line supplied with a first voltage and the first transistor,

wherein the first transistor is coupled between the second transistor and a second line supplied with a second voltage different from the first voltage,

wherein a polarity of the first transistor is opposite to a polarity of the second transistor,

wherein a gate of the second transistor is configured to receive a bias voltage,

wherein a first output signal is configured to output from a second node between the first transistor and the second transistor,

wherein the comparator comprises a third transistor coupled to a third line supplied with a third voltage, and a gate of the third transistor is configured to receive the first output signal, and

wherein the comparator comprises a fourth transistor coupled to the third transistor and a switch coupled between a gate and a drain of the fourth transistor.

11. The light detecting device of claim 10 , wherein a third capacitor is coupled between the gate of the fourth transistor and the first voltage.

12. The light detecting device of claim 10 , wherein a second output signal is configured to output from a node between the third transistor and the fourth transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2021
From: NIWA, ATSUMI; YAMASHITA, TOMONORI; MOUE, TAKASHI; UENO, YOSUKE
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 057572/0034 →
Priority Claims (2)
JP 2017-039337 · Mar 2, 2017 · national
JP 2017-117453 · Jun 15, 2017 · national
Continuity (2)
Continuation 16488734
Related Publication 20210368125A1 · Nov 25, 2021