Error correction of memory

1. A memory comprising:

a data receiving circuit suitable for receiving data during a write operation;

a data rotation circuit suitable for changing an order of the data transferred from the data receiving circuit and outputting the data having an order changed in response to an address during the write operation;

an error correction code generation circuit suitable for generating an error correction code based on the data output from the data rotation circuit during the write operation;

a memory core suitable for storing a) the data received by the data receiving circuit and b) the error correction code based on the data output from the data rotation circuit during the write operation,

wherein the data rotation circuit changes the order of the data read from the memory core and outputs the data having the order changed in response to the address during a read operation, and

the memory further comprises:

an error correction circuit suitable for correcting an error of the data read from the memory core based on the data output from the data rotation circuit and the error correction code read from the memory core during the read operation.

2. The memory of claim 1 , further comprising:

a data transferring circuit suitable for outputting error-corrected data corrected by the error correction circuit.

3. The memory of claim 1 , wherein the address is a portion of bits of a row address.

4. The memory of claim 3 , wherein the data rotation circuit shifts the order of the data input to the data rotation circuit according to a level of the portion of the bits of the row address and outputs the shifted data, or outputs the data input to the data rotation circuit without any shift.

5. The memory of claim 3 , wherein the error correction circuit is capable of

a) correcting a 1-bit error occurring in the data read from the memory core, and

b) correcting errors in some cases and miscorrecting the errors in other cases, among cases when an error of 2 consecutive bits occurs in the data read from the memory core.

6. The memory of claim 3 , wherein the error correction circuit is capable of

a) correcting a 1-bit error occurring in the data read from the memory core, and

b) not miscorrecting errors in some cases and miscorrecting the errors in other cases, among cases when an error of 2 consecutive bits occurs in the data read from the memory core.

7. A memory comprising:

a data receiving circuit suitable for receiving write data including a plurality of bits for a write operation;

a data rotation circuit suitable for selectively changing an order of the plurality of bits in the write data based on an address associated with the write data to generate write output data;

an error correction code generation circuit suitable for generating an error correction code based on the write output data;

a memory core suitable for storing the write output data and the error correction code; and

an error correction circuit receives, from the memory core, read data including multiple bits and the error correction code,

wherein the data rotation circuit receives the read data from the memory core and selectively changes the order of the multiple bits in the read data based on an address associated with the read data to generate read output data, and

wherein the error correction circuit corrects an error of the read data based on the read output data and the error correction code.