Electrostatic discharge protection circuit having time-extended discharging mechanism
The present invention discloses an electrostatic discharge protection circuit having time-extended discharging mechanism. A RC circuit is coupled between an ESD input terminal that receives an ESD input and a ground terminal and includes an input control terminal. An inverter includes a P-type transistor coupled between the ESD input terminal and an output control terminal and an N-type transistor circuit including N-type transistors coupled in series and between the output control terminal and a ground terminal, wherein two of the N-type transistors has an internal connection terminal. Gates of the P-type transistor and N-type transistors are controlled by the input control terminal. A switch transistor is coupled between the ESD input terminal and the internal connection terminal. A discharging transistor is coupled between the ESD input terminal and the ground terminal. The gates of the switch transistor and the discharging transistor are controlled by the output control terminal.
1. An electrostatic discharge protection circuit having time-extended discharging mechanism comprising:
a RC circuit electrically coupled between an ESD input terminal and a ground terminal and comprising an input control terminal, wherein a voltage level of the ESD input terminal is predetermined to be at a low state level and is configured to receive an ESD input;
an inverter comprising:
a P-type transistor electrically coupled between the ESD input terminal and an output control terminal; and
an N-type transistor circuit comprising a plurality of N-type transistors electrically coupled in series between the output control terminal and the ground terminal, wherein two of the N-type transistors comprise an internal connection terminal, and a gate of each of the P-type transistor and the N-type transistors is controlled by the input control terminal;
a switch transistor electrically coupled between the ESD input terminal and the internal connection terminal, wherein the switch transistor comprises a plurality of transistors electrically coupled in series; and
a discharging transistor electrically coupled between the ESD input terminal and the ground terminal, wherein a gate of each of the switch transistor and the discharging transistor is controlled by the output control terminal.
2. The electrostatic discharge protection circuit of claim 1 , wherein when the ESD input terminal receives the ESD input, the voltage level of the ESD input terminal increases from the low state level to a high state level and a voltage level of the input control terminal is kept to be at the low state level within a predetermined time so as to make a voltage level of the output control terminal increases to the high state level through the inverter;
wherein the output control terminal turns on the switch transistor such that a voltage level of the internal connection terminal increases to the high state level to turn off the N-type transistor circuit to further keep the voltage level of the output control terminal at the high state level, and the output control terminal turns on the discharging transistor to discharge the ESD input terminal.
3. The electrostatic discharge protection circuit of claim 2 , wherein the voltage level of the input control terminal increases to the high state level after the predetermined time, and the switch transistor is kept to be turned on to keep the voltage level of the internal connection terminal at the high state level so as to turn off the N-type transistor circuit, to keep the voltage level of the output control terminal at the high state level such that the discharging transistor turns on to discharge the ESD input terminal.
4. The electrostatic discharge protection circuit of claim 3 , when the voltage level of the ESD input terminal is discharged to be at the low state level, the switch transistor fails to keep the internal connection terminal at the high state level such that the N-type transistor circuit turns on according to the input control terminal to decrease the voltage level of the output control terminal to the low state level to further turn off the discharging transistor and the switch transistor.
5. The electrostatic discharge protection circuit of claim 1 , wherein the RC circuit comprises:
a resistor electrically coupled between the ESD input terminal and the input control terminal; and
a capacitor electrically coupled between the input control terminal and the ground terminal;
wherein the predetermined time is determined by a time constant of the resistor and the capacitor.
6. The electrostatic discharge protection circuit of claim 5 , wherein the resistor is a transistor resistor, a poly-Si resistor or an N-type well resistor.
7. The electrostatic discharge protection circuit of claim 5 , wherein the capacitor is a metal-oxide-semiconductor capacitor, a metal-oxide-metal capacitor or a metal-insulator-metal capacitor.
8. The electrostatic discharge protection circuit of claim 1 , wherein the discharging transistor comprises an N-type transistor or a P-type transistor electrically coupled to the output control terminal through an additional inverter.
9. The electrostatic discharge protection circuit of claim 1 , wherein the switch transistor comprises an N-type transistor or a P-type transistor electrically coupled to the output control terminal through an additional inverter.