IP Library › Granted Patent US 11,699,727
Granted Patent B2
US 11,699,727 · App. 17/329,212 · Granted Jul 11, 2023

Semiconductor device

Inventors: Makoto Shimosawa (Matsumoto, JP); Takeyoshi Nishimura (Matsumoto, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L29/41708H01L27/0664H01L29/1095H01L29/407H01L29/45H01L29/7397H01L29/8613
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Quick Facts
Patent No.
US 11,699,727
App. No.
17/329,212
Granted
Jul 11, 2023
Kind
B2
Abstract

Provided is a semiconductor device including: a drift region of first conductivity type provided in a semiconductor substrate; a base region of second conductivity type provided in the semiconductor substrate; an emitter region of first conductivity type provided at a front surface of the semiconductor substrate; a contact region of second conductivity type provided on the base region and having a higher doping concentration than the base region; a contact trench portion provided at the front surface of the semiconductor substrate; a first barrier layer provided at a side wall and a bottom surface of the contact trench portion; and a second barrier layer provided in contact with the contact region at the side wall of the contact trench portion.

Claims (31)

1. A semiconductor device comprising:

a drift region of first conductivity type provided in a semiconductor substrate;

a base region of second conductivity type provided in the semiconductor substrate;

an emitter region of first conductivity type provided at a front surface of the semiconductor substrate;

a contact region of second conductivity type provided on the base region and having a higher doping concentration than the base region;

a contact trench portion provided at the front surface of the semiconductor substrate;

a first barrier layer provided at a side wall and a bottom surface of the contact trench portion; and

a second barrier layer provided in contact with the contact region at the side wall of the contact trench portion, wherein

the second barrier layer is a silicon oxide film, and

a contact resistance between the second barrier layer and the emitter region is 100Ω or less.

2. The semiconductor device according to claim 1 , wherein the second barrier layer is provided in contact with the emitter region at the side wall of the contact trench portion.

3. The semiconductor device according to claim 1 , wherein the second barrier layer has a film thickness of 1 nm or more and 50 nm or less.

4. The semiconductor device according to claim 2 , wherein the second barrier layer has a film thickness of 1 nm or more and 50 nm or less.

5. The semiconductor device according to claim 1 , wherein a conductivity of the second barrier layer is the same as or lower than a conductivity of the first barrier layer.

6. The semiconductor device according to claim 2 , wherein a conductivity of the second barrier layer is the same as or lower than a conductivity of the first barrier layer.

7. The semiconductor device according to claim 1 , wherein the first barrier layer contains at least any of Ti, TiN, Ta or TaN.

8. The semiconductor device according to claim 1 , wherein the first barrier layer includes a silicide region which has been solicited at the bottom surface of the contact trench portion.

9. The semiconductor device according to claim 1 , wherein the contact trench portion is arranged in a stripe pattern between and along a plurality of trench portions, the plurality of trench portions being arranged in a predetermined arrangement direction at the side of the front surface of the semiconductor substrate.

10. The semiconductor device according to claim 1 , wherein the contact trench portion is arranged in a matrix form between a plurality of trench portions arranged in a grid at the side of the front surface of the semiconductor substrate.

11. The semiconductor device according to claim 1 , wherein the contact trench portion is arranged in a grid between and along a plurality of trench portions, the plurality of trench portions being arranged in a matrix form at the side of the front surface of the semiconductor substrate.

12. A semiconductor device, comprising:

a drift region of first conductivity type provided in a semiconductor substrate;

a base region of second conductivity type provided in the semiconductor substrate;

an emitter region of first conductivity type provided at a front surface of the semiconductor substrate;

a contact region of second conductivity type provided on the base region and having a higher doping concentration than the base region;

a contact trench portion provided at the front surface of the semiconductor substrate;

a first barrier layer provided at a side wall and a bottom surface of the contact trench portion; and

a second barrier layer provided in direct contact with the contact region at the side wall of the contact trench portion,

wherein the first barrier layer is provided in direct contact with the emitter region at the side wall of the contact trench portion.

13. The semiconductor according to claim 12 , wherein the second barrier layer has a film thickness of 1 nm or more and 50 nm or less.

14. The semiconductor device according to claim 12 , wherein a conductivity of the second barrier layer is the same as or lower than a conductivity of the first barrier layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2021
From: SHIMOSAWA, MAKOTO; NISHIMURA, TAKEYOSHI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 056336/0591 →
Priority Claims (1)
JP 2020-119805 · Jul 13, 2020 · national
Continuity (1)
Related Publication 20220013645A1 · Jan 13, 2022