Compiler-based code generation for post-silicon validation

1. A computer system comprising:

one or more processing devices configured to validate operation of a device-under-test (DUT) through post-silicon validation testing;

one or more memory devices communicatively coupled to the one or more processing devices; and

a compiler communicatively coupled to the one or more processing devices and the one or more memory devices, the one or more processing devices configured to:

generate a test program through the DUT, comprising:

generate a plurality of memory intervals;

inject the plurality of memory intervals into the test program;

inject, from the compiler, a plurality of compiled test snippets into the test program; and

execute one or more post-silicon validation tests for the DUT with the test program.

2. The system of claim 1 , the one or more processing devices further configured to:

generate, through the compiler, compiler-based code configured for parallel execution within the DUT.

3. The system of claim 1 , the one or more processing devices further configured to:

generate, through the compiler, the plurality of compiled test snippets through a call injected into the test program.

4. The system of claim 1 , the one or more processing devices further configured to:

inject the plurality of memory intervals randomly.

5. The system of claim 1 , the one or more processing devices further configured to:

combine instructions generated through a statement with assembly code produced by the compiler from a higher-level language.

6. The system of claim 1 , wherein the compiler is positioned off-DUT, the one or more processing devices further configured to:

inject the compiled test snippets into the test program concurrently with the executing one or more post-silicon validation tests for the DUT.

7. The system of claim 1 , wherein the compiler is positioned on-DUT, the one or more processing devices further configured to:

inject the compiled test snippets into the test program concurrently with the executing one or more post-silicon validation tests for the DUT.

8. A computer program product, comprising:

one or more computer readable storage media; and

program instructions collectively stored on the one or more computer storage media, the program instructions comprising:

program instructions to execute one or more post-silicon validation tests for a device-under-test (DUT) comprising:

program instructions to generate a test program through the DUT, comprising:

program instructions to generate a plurality of memory intervals;

program instructions to inject the plurality of memory intervals into the test program;

program instructions to inject a plurality of compiled test snippets into the test program; and

program instructions to execute one or more post-silicon validation tests for the DUT with the test program.

9. The computer program product of claim 8 , further comprising:

program instructions to generate compiler-based code configured for parallel execution within the DUT.

10. The computer program product of claim 8 , further comprising:

program instructions to generate the plurality of compiled test snippets through a call injected into the test program; and

program instructions to inject the plurality of memory intervals randomly.

11. The computer program product of claim 8 , further comprising:

program instructions to combine instructions generated through a statement with assembly code produced by a compiler from a higher-level language.

12. The computer program product of claim 8 , further comprising:

program instructions to inject the compiled test snippets into the test program concurrently with the executing one or more post-silicon validation tests for the DUT, wherein the compiler is positioned off-DUT.

13. The computer program product of claim 8 , further comprising:

program instructions to inject the compiled test snippets into the test program concurrently with the executing one or more post-silicon validation tests for the DUT, wherein the compiler is positioned on-DUT.

14. A computer-implemented method comprising:

generating a test program through a device-under-test (DUT), comprising:

generating a plurality of memory intervals;

injecting the plurality of memory intervals into the test program;

injecting a plurality of compiled test snippets into the test program; and

executing one or more post-silicon validation tests for the DUT with the test program.

15. The method of claim 14 , wherein the injecting a plurality of compiled test snippets into the test program comprises:

generating compiler-based code configured for parallel execution within the DUT.

16. The method of claim 14 , wherein the injecting a plurality of compiled test snippets into the test program further comprises:

generating the plurality of compiled test snippets through a call injected into the test program.

17. The method of claim 14 , wherein the injecting the plurality of compiled test snippets into the test program further comprises:

injecting the plurality of memory intervals into the test program randomly.

18. The method of claim 14 , wherein the injecting a plurality of compiled test snippets into the test program further comprises:

combining instructions generated through a statement with assembly code produced by a compiler from a higher-level language.

19. The method of claim 14 , wherein the injecting a plurality of compiled test snippets into the test program further comprises:

injecting the compiled test snippets into to the test program concurrently with the executing one or more post-silicon validation tests for the DUT, wherein the compiler is positioned off-DUT.

20. The method of claim 14 , wherein the injecting a plurality of compiled test snippets into the test program further comprises:

injecting the compiled test snippets into the test program concurrently with the executing one or more post-silicon validation tests for the DUT, wherein the compiler is positioned on-DUT.