IP Library › Granted Patent US 11,825,704
Granted Patent B2
US 11,825,704 · App. 17/331,606 · Granted Nov 21, 2023

Display apparatus having flourine at interfaces of semiconductor layer and manufacturing method thereof

Inventors: Moonsung Kim (Yongin-si, KR); Younggil Park (Yongin-si, KR); Jaebum Han (Yongin-si, KR); Sooim Jeong (Yongin-si, KR)
Assignee: Samsung Display Co., Ltd.
H10K59/124H10K71/00
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Quick Facts
Patent No.
US 11,825,704
App. No.
17/331,606
Granted
Nov 21, 2023
Kind
B2
Abstract

An embodiment of a display apparatus includes a substrate, a buffer layer on the substrate, a thin film transistor including a semiconductor layer disposed on the buffer layer and including a silicon semiconductor, and a gate electrode insulated from the semiconductor layer, and an insulating layer covering the semiconductor layer, in which a concentration of fluorine at an interface between the semiconductor layer and the buffer layer is at least 10% of a concentration of the fluorine at the interface between the semiconductor layer and the insulating layer.

Claims (21)

1. A display apparatus comprising:

a substrate;

a buffer layer on the substrate;

a thin film transistor comprising a semiconductor layer disposed on the buffer layer and comprising a silicon semiconductor, and a gate electrode insulated from the semiconductor layer; and

an insulating layer covering the semiconductor layer,

wherein a concentration of fluorine at an interface between the semiconductor layer and the buffer layer is at least 10% of a concentration of the fluorine at the interface between the semiconductor layer and the insulating layer.

2. The display apparatus of claim 1 , wherein a minimum concentration of the fluorine in the first semiconductor layer is no more than 1×10 20 atom/cm 3 .

3. The display apparatus of claim 2 , wherein a concentration of the fluorine at the interface between the semiconductor layer and the buffer layer is greater than a minimum concentration of the fluorine of the semiconductor layer.

4. The display apparatus of claim 1 , wherein the buffer layer comprises a first buffer layer on the substrate, a second buffer layer on the first buffer layer, and a third buffer layer on the second buffer layer, and

a hydrogen concentration of the first buffer layer is greater than a hydrogen concentration of the second buffer layer.

5. The display apparatus of claim 4 , wherein a hydrogen concentration of the first buffer layer is within the range and including 1.1×10 22 atom/cm 3 to 2.0×10 22 atom/cm 3 , and a hydrogen concentration of the second buffer layer is within the range and including 7.0×10 21 atom/cm 3 to 1.0×10 22 atom/cm 3 .

6. The display apparatus of claim 4 , wherein a film density of the first buffer layer is greater than a film density of the second buffer layer.

7. The display apparatus of claim 4 , further comprising a barrier layer disposed between the substrate and the buffer layer and comprising a first layer on the substrate, a second layer on the first layer, and a third layer on the second layer.

8. The display apparatus of claim 7 , wherein the second layer has a surface roughness within the range and including 3 nm to 5 nm.

9. The display apparatus of claim 7 , wherein a hydrogen concentration of the second layer is greater than a hydrogen concentration of the first layer.

10. The display apparatus of claim 9 , wherein the first layer has a first thickness in a direction perpendicular to the substrate, and the third layer has a second thickness in a direction perpendicular to the substrate.

11. The display apparatus of claim 10 , wherein the first thickness and the second thickness each are within the range and including 50 Å to 300 Å.

12. The display apparatus of claim 1 , further comprising:

a second insulating layer covering the gate electrode; and

a second thin film transistor disposed on the second insulating layer and comprising a second semiconductor layer including an oxide semiconductor and a second gate electrode insulated from the second semiconductor layer.

13. The display apparatus of claim 12 , wherein the gate electrode and the second gate electrode are arranged on layers different from each other.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 26, 2021
From: KIM, MOONSUNG; PARK, YOUNGGIL; HAN, JAEBUM; JEONG, SOOIM
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 056365/0193 →
Priority Claims (1)
KR 10-2020-0168716 · Dec 4, 2020 · national
Continuity (1)
Related Publication 20220181416A1 · Jun 9, 2022