IP Library › Granted Patent US 11,776,743
Granted Patent B2
US 11,776,743 · App. 17/332,608 · Granted Oct 3, 2023

Multilayer capacitor and board having the same mounted thereon

Inventors: Hyung Joon Kim (Suwon-si, KR); Hyun Ju Kim (Suwon-si, KR); Kyoung Ae Kim (Suwon-si, KR)
Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
H01G4/005H01G2/065H01G4/30
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Quick Facts
Patent No.
US 11,776,743
App. No.
17/332,608
Granted
Oct 3, 2023
Kind
B2
Abstract

A multilayer capacitor includes a capacitor body including a dielectric layer and first and second internal electrodes and having first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first and second surfaces, connected to the third and fourth surfaces, and opposing each other, first and second side portions disposed on the fifth and sixth surfaces of the capacitor body, respectively, and first and second external electrodes disposed on the third and fourth surfaces of the capacitor body, respectively, and connected to the first and second internal electrodes, respectively. The first and second internal electrodes have protrusions at one-side edge in a direction perpendicular to the fifth and sixth surfaces of the capacitor body.

Claims (68)

1. A multilayer capacitor comprising:

a capacitor body including a dielectric layer and first and second internal electrodes, the capacitor body including first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first and second surfaces, connected to the third and fourth surfaces, and opposing each other in a width direction of the capacitor body;

first and second side portions disposed on the fifth and sixth surfaces of the capacitor body, respectively; and

first and second external electrodes disposed on the third and fourth surfaces of the capacitor body, respectively, and connected to the first and second internal electrodes, respectively,

wherein the first and second internal electrodes each have protrusions and grooves at edges opposing each other in the width direction.

2. The multilayer capacitor of claim 1 , wherein the protrusions of the first and second internal electrodes are in contact with one of the first and second side portions.

3. The multilayer capacitor of claim 1 , wherein the protrusions of the first internal electrode and the protrusions of the second internal electrode alternate with each other in a direction in which the first and second internal electrodes are stacked.

4. The multilayer capacitor of claim 1 , wherein the protrusions of the first internal electrode, contact one of the first and second side portions, and

the protrusions of the second internal electrode contact the one of the first and second side portions.

5. The multilayer capacitor of claim 4 , wherein the protrusions of the first internal electrode have a predetermined interval therebetween, and the protrusions of the second internal electrode have a predetermined interval therebetween.

6. The multilayer capacitor of claim 1 , wherein the first internal electrode comprises first grooves spaced apart from the fifth and sixth surfaces of the capacitor body, and

the second internal electrode comprises third grooves spaced apart from the fifth and sixth surfaces of the capacitor body.

7. The multilayer capacitor of claim 6 , further comprising:

first dummy patterns respectively disposed in the first grooves to be spaced apart from the first internal electrode, and

third dummy patterns respectively disposed in the third grooves to be spaced apart from the second internal electrode.

8. The multilayer capacitor of claim 7 , wherein the first dummy patterns are in contact with one of the first and second side portions, and

the third dummy patterns are in contact with the one of the first and second side portions.

9. The multilayer capacitor of claim 6 , wherein one of the first grooves is disposed in a portion of the first internal electrode connecting the third and fifth surfaces of the capacitor body, and

one of the third grooves is disposed in a portion of the second internal electrode connecting the fourth and fifth surfaces of the capacitor body.

10. The multilayer capacitor of claim 6 , wherein the first grooves have a predetermined interval therebetween, and the third grooves have a predetermined interval therebetween.

11. The multilayer capacitor of claim 1 , wherein the first internal electrode has a first cutout disposed at a corner adjacent to the fourth surface of the capacitor, and

the second internal electrode has a second cutout disposed a corner adjacent to the third surface of the capacitor.

12. The multilayer capacitor of claim 1 , wherein the capacitor body includes an active region in which the first and second internal electrodes overlap, and upper and lower cover regions disposed on upper and lower surfaces of the active region, respectively.

13. The multilayer capacitor of claim 1 , wherein the first and second external electrodes include, respectively:

first and second connecting portions disposed on the third and fourth surfaces of the capacitor body, respectively, and connected to the first and second internal electrodes, respectively; and

first and second band portions extending from the first and second connecting portions to a portion of the first surface of the capacitor body, respectively.

14. The multilayer capacitor of claim 1 , wherein the protrusions of the first internal electrode and the protrusions of the second internal electrode are disposed to alternate with each other in a direction in which the first and second internal electrodes are stacked,

the first internal electrode has a first cutout disposed at a corner adjacent to the fourth surface of the capacitor body, and

the second internal electrode has a second cutout disposed at a corner adjacent to the third surface of the capacitor body.

15. The multilayer capacitor of claim 1 , wherein the protrusions of the first internal electrode and the protrusions of the second internal electrode are disposed to alternate with each other in a direction in which the first and second internal electrodes are stacked,

the protrusions of the first internal electrode contact one of the first and second side portions, and

the protrusions of the second internal electrode contact the one of the first and second side portions.

16. The multilayer capacitor of claim 15 , wherein the first internal electrode has first grooves spaced apart from the fifth and sixth surfaces of the capacitor body, and

the second internal electrode has third grooves spaced apart from the fifth and sixth surfaces of the capacitor body.

17. The multilayer capacitor of claim 15 , wherein the first internal electrode has a first cutout disposed a corner adjacent to the fourth surface of the capacitor body, and

the second internal electrode has a second cutout disposed at a corner adjacent to the third surface of the capacitor body.

18. The multilayer capacitor of claim 1 , wherein the first and second internal electrodes have protrusions at the other of edges opposing each other in the width direction.

19. A board having a multilayer capacitor mounted thereon, the board comprising:

a substrate having first and second electrode pads on one surface; and

the multilayer capacitor of claim 1 , mounted in such a manner that first and second external electrodes are connected to the first and second electrode pads, respectively.

20. A multilayer capacitor comprising:

a capacitor body including a dielectric layer and first and second internal electrodes; and

first and second external electrodes respectively disposed on surfaces of the capacitor body opposing each other in a length direction of the capacitor body, and respectively connected to the first and second internal electrodes,

wherein an edge of one of the first and second internal electrodes has protrusions and grooves disposed in the length direction, and

the protrusions and grooves are spaced apart from the first and second external electrodes.

21. The multilayer capacitor of claim 20 , further comprising a side portion disposed on the capacitor body to contact the edge of the one of the first and second internal electrodes.

22. The multilayer capacitor of claim 20 , wherein the protrusions and grooves alternately disposed along the edge.

23. The multilayer capacitor of claim 22 , further comprising:

dummy patterns respectively disposed in the grooves to be spaced apart from the one of the first and second internal electrodes.

24. The multilayer capacitor of claim 22 , further comprising:

a side portion disposed on the capacitor body to contact the edge of the one of the first and second internal electrodes; and

dummy patterns respectively disposed in the grooves to be spaced apart from the one of the first and second internal electrodes and contacting the side portion.

25. The multilayer capacitor of claim 22 , wherein a width, in the length direction, of one of the grooves is greater than a width, in the length direction, of one of the protrusions.

26. The multilayer capacitor of claim 20 , wherein an end of the edge of the one of the first and second internal electrodes is provided with a groove or a cutout recessed from a corner of the one of the first and second internal electrodes.

27. A multilayer capacitor comprising:

a capacitor body including first and second internal electrodes and a dielectric layer disposed therebetween; and

first and second external electrodes respectively disposed on surfaces of the capacitor body opposing each other in a length direction of the capacitor body, and respectively connected to the first and second internal electrodes,

wherein one of the first internal electrodes and one of the second internal electrodes each have an edge provided with protrusions and grooves disposed in the length direction.

28. The multilayer capacitor of claim 27 , wherein the protrusions and grooves are alternately disposed along the length direction.

29. The multilayer capacitor of claim 28 , further comprising:

first dummy patterns respectively disposed in the grooves of the one of the first internal electrodes to be spaced apart from the one of the first internal electrodes; and

third dummy patterns respectively disposed in the grooves of the one of the second internal electrodes to be spaced apart from the one of the second internal electrodes.

30. The multilayer capacitor of claim 28 , wherein the protrusions of the one of the first internal electrodes respectively overlap with the grooves of the one of the second internal electrodes in a stacking direction of the first and second internal electrodes, and

the grooves of the one of the first internal electrodes respectively overlap with the protrusions of the one of the second internal electrodes in the stacking direction of the first and second internal electrodes.

31. The multilayer capacitor of claim 28 , wherein a width, in the length direction, of one of the grooves of the one of the first internal electrodes is greater than a width in, the length direction, of one of the protrusions of the one of the second internal electrodes which overlaps with the one of the grooves of the one of the first internal electrodes in a stacking direction of the first and second internal electrodes, and

a width, in the length direction, of one of the grooves of the one of the second internal electrodes is greater than a width, in the length direction, of one of the protrusions of the one of the first internal electrodes which overlaps with the one of the grooves of the one of the second internal electrodes in the stacking direction of the first and second internal electrodes.

32. The multilayer capacitor of claim 27 , wherein an end of the edge of the one of the first internal electrodes is provided with a groove and an end of the edge of the one of the second internal electrodes is provided with a cutout, and

the groove at the end of the edge of the one of the first internal electrodes and the cutout at the end of the edge of the one of the second internal electrodes overlap with each other in a stacking direction of the first and second internal electrodes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2021
From: KIM, HYUNG JOON; KIM, HYUN JU; KIM, KYOUNG AE
To: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Reel/Frame 056378/0738 →
Priority Claims (1)
KR 10-2020-0150593 · Nov 12, 2020 · national
Continuity (1)
Related Publication 20220148803A1 · May 12, 2022
Cited By (1)
US 12,744,156