Echo estimation system and echo estimation method

1. An echo estimation system comprising:

a transceiver circuitry; and

a processor circuitry coupled to the transceiver circuitry, wherein the processor circuitry is configured to calculate linear echo power and non-linear echo power based on a signal under test in the transceiver circuitry, wherein the linear echo power and the non-linear echo power are utilized to determine a quality of the transceiver circuitry or utilized to determine component parameters of the transceiver circuitry, wherein the processor circuitry comprises:

a signal averaging circuit configured to generate an averaged echo signal based on the signal under test;

a high-pass filter configured to generate a filtered echo signal based on the averaged echo signal; and

an echo estimation circuit configured to generate a linear echo signal based on a preset signal and the filtered echo signal.

2. The echo estimation system of claim 1 , wherein the transceiver circuitry comprises:

a signal generating circuit configured to generate the preset signal, wherein the transceiver circuitry generates the signal under test based on the preset signal.

3. The echo estimation system of claim 1 , wherein the echo estimation circuit is further configured to generate an aligned preset signal based on the preset signal and the filtered echo signal, generate an echo estimator coefficient based on the aligned preset signal and the filtered echo signal, and generate the linear echo signal based on the aligned preset signal and the echo estimator coefficient.

4. The echo estimation system of claim 1 , wherein the processor circuitry is further configured to generate a non-linear echo signal based on the filtered echo signal and the linear echo signal.

5. The echo estimation system of claim 4 , wherein the processor circuitry further comprises:

an adder configured to calculate a difference between the filtered echo signal and the linear echo signal as the non-linear echo signal.

6. The echo estimation system of claim 4 , wherein the processor circuitry is further configured to calculate the linear echo power based on the linear echo signal, and calculate a linear echo return loss based on the linear echo power and power on a media dependent interface, wherein the processor circuitry is further configured to generate the non-linear echo power based on the non-linear echo signal, and calculate a non-linear echo return loss based on the non-linear echo power and the power on the media dependent interface, wherein the linear echo return loss or the non-linear echo return loss is utilized to determine the quality of the transceiver circuitry or utilized to determine the component parameters of the transceiver circuitry.

7. The echo estimation system of claim 6 , wherein the power on the media dependent interface is measured under a first condition or a second condition, wherein the first condition is that the transceiver circuitry is coupled to another transceiver circuitry, and the second condition is that the transceiver circuitry is coupled to a resistor.

8. The echo estimation system of claim 6 , wherein the linear echo return loss and the non-linear echo return loss are utilized to determine whether a circuit corresponding to the signal under test in the transceiver circuitry is abnormal or not.

9. The echo estimation system of claim 1 , wherein the transceiver circuitry comprises a plurality of receiving-end interfaces, and the signal under test is generated on one of the receiving-end interfaces.

10. An echo estimation method comprising:

generating a signal under test by a transceiver circuitry; and

calculating linear echo power and non-linear echo power based on the signal under test by a processor circuitry, wherein the linear echo power and the non-linear echo power are utilized to determine a quality of the transceiver circuitry or utilized to determine component parameters of the transceiver circuitry, wherein calculating the linear echo power based on the signal under test by the processor circuitry comprises:

generating an averaged echo signal based on the signal under test by a signal averaging circuit of the processor circuitry;

generating a filtered echo signal based on the averaged echo signal by a high-pass filter of the processor circuitry; and

generating a linear echo signal based on a preset signal and the filtered echo signal by an echo estimation circuit of the processor circuitry.

11. The echo estimation method of claim 10 , wherein generating the signal under test by the transceiver circuitry comprises:

generating the preset signal by a signal generating circuit of the transceiver circuitry, wherein the transceiver circuitry generates the signal under test based on the preset signal.

12. The echo estimation method of claim 10 , wherein generating the linear echo signal based on the preset signal and the filtered echo signal by the echo estimation circuit further comprises:

generating an aligned preset signal based on the preset signal and the filtered echo signal by the echo estimation circuit;

generating an echo estimator coefficient based on the aligned preset signal and the filtered echo signal by the echo estimation circuit; and

generating the linear echo signal based on the aligned preset signal and the echo estimator coefficient by the echo estimation circuit.

13. The echo estimation method of claim 10 , further comprising:

generating a non-linear echo signal based on the filtered echo signal and the linear echo signal by the processor circuitry.

14. The echo estimation method of claim 13 , wherein generating the non-linear echo signal based on the filtered echo signal and the linear echo signal by the processor circuitry further comprises:

calculating a difference between the filtered echo signal and the linear echo signal as the non-linear echo signal by an adder.

15. The echo estimation method of claim 13 , further comprising:

calculating the linear echo power based on the linear echo signal by the processor circuitry;

calculating a linear echo return loss based on the linear echo power and power on a media dependent interface by the processor circuitry;

generating the non-linear echo power based on the non-linear echo signal by the processor circuitry; and

calculating a non-linear echo return loss based on the non-linear echo power and the power on the media dependent interface by the processor circuitry,

wherein the linear echo return loss or the non-linear echo return loss is utilized to determine the quality of the transceiver circuitry or utilized to determine the component parameters of the transceiver circuitry.

16. The echo estimation method of claim 15 , wherein the power on the media dependent interface is measured under a first condition or a second condition, wherein the first condition is that the transceiver circuitry is coupled to another transceiver circuitry, and the second condition is that the transceiver circuitry is coupled to a resistor.

17. The echo estimation method of claim 15 , wherein the linear echo return loss and the non-linear echo return loss are utilized to determine whether a circuit corresponding to the signal under test in the transceiver circuitry is abnormal or not.

18. The echo estimation method of claim 10 , wherein the transceiver circuitry comprises a plurality of receiving-end interfaces, and the signal under test is generated on one of the receiving-end interfaces.