On-chip antenna and on-chip antenna array
An on-chip antenna comprising an electrically insulating substrate having first and second faces; a metal layer arranged on the second face; and, a dipole antenna structure arranged on the first face, the dipole antenna structure comprising a dipole antenna and a feed structure connected to the dipole antenna; the on-chip antenna being configured such that when the feed structure is fed with an electrical signal it operates simultaneously in (i) at least one dielectric resonator mode to function as a dielectric resonance antenna, and (ii) at least one dipole mode to function as a cavity backed dipole antenna.
1. An on-chip antenna comprising:
an electrically insulating substrate having first and second faces;
a metal layer arranged on the second face; and,
a dipole antenna structure arranged on the first face, the dipole antenna structure comprising a dipole antenna and a feed structure connected to the dipole antenna;
the on-chip antenna being configured such that when the feed structure is fed with an electrical signal it operates simultaneously in (i) at least one dielectric resonator mode to function as a dielectric resonance antenna, and (ii) at least one dipole mode to function as a cavity backed dipole antenna.
2. An on-chip antenna as claimed in claim 1 , wherein the feed structure comprises a co-planar waveguide.
3. An on-chip antenna as claimed in claim 2 wherein the coplanar waveguide and dipole antenna are coplanar.
4. An on-chip antenna as claimed in claim 2 , wherein the coplanar waveguide and dipole antenna lie in different planes separated by a passivation layer.
5. An on-chip antenna as claimed in claim 1 , wherein the dipole antenna comprises at least one comb shaped dipole element, the comb shaped dipole element comprising a base and a plurality of substantially parallel fingers extending from the base.
6. An on-chip antenna as claimed in claim 5 , wherein the length of the fingers increases towards the center of the base.
7. An on-chip antenna as claimed in claim 5 , wherein the base is curved.
8. An on-chip antenna as claimed in claim 5 , wherein the comb shaped dipole element has a mirror symmetry about a symmetry axis in a plane parallel to the first face.
9. An on-chip antenna as claimed in claim 5 , comprising two comb shaped dipole elements arranged back to back.
10. An on-chip antenna as claimed in claim 9 , wherein the dipole antenna has a mirror symmetry about first and second symmetry axes, the second symmetry axis being normal to the first.
11. An on-chip antenna as claimed in claim 1 , wherein the substrate comprises a silicon layer.
12. An on-chip antenna as claimed in claim 11 , wherein the substrate further comprises a silicon dioxide layer.
13. An on-chip antenna as claimed in claim 1 , further comprising a signal source connected to the feed structure and configured to provide a signal at wavelength λ.
14. An on-chip antenna as claimed in claim 13 , wherein the thickness of the substrate is in the range 0.6λ to 0.8λ.
15. An on-chip antenna as claimed in claim 13 , wherein the distance between the dipole antenna and the edge of the substrate is in the range 0.6λ to 0.8λ.
16. An on-chip antenna as claimed in claim 1 , wherein the substrate and dipole antenna structure are dimensioned for mm wave or THz operations.
17. An on-chip antenna as claimed in claim 1 further comprising at least one separator arranged in or around the substrate, the separator having a dielectric permittivity lower than that of the substrate.
18. An on-chip antenna as claimed in claim 17 , wherein the separator is an air gap.
19. An on-chip antenna array comprising:
a plurality of on-chip antennae, each on chip antenna comprising
an electrically insulating substrate having first and second faces;
a metal layer arranged on the second face; and,
a dipole antenna structure arranged on the first face, the dipole antenna structure comprising a dipole antenna and a feed structure connected to the dipole antenna;
the on-chip antenna being configured such that when the feed structure is fed with an electrical signal it operates simultaneously in (i) at least one dielectric resonator mode to function as a dielectric resonance antenna, and (ii) at least one dipole mode to function as a cavity backed dipole antenna
the antennae being arranged on a common base layer in an n*m array where n and m are positive integers;
each substrate being separated from the adjacent substrate by a separator having a dielectric permittivity lower than that of the substrate.
20. An on-chip antenna array as claimed in claim 19 wherein the separator is an air gap.