Fully self-aligned subtractive etch
Apparatuses and methods to provide fully self-aligned first metallization lines, M1, via, and second metallization lines, M2, are described. A first metallization line comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate; a second metallization line comprising a set of second conductive lines on an etch stop layer above the first metallization line, the set of second conductive lines extending along a second direction that crosses the first direction at an angle; and at least one via between the first metallization line and the second metallization line, the at least one via comprising a via metallization layer, wherein the at least one via is self-aligned along the second direction to one of the first metallization lines and the at least one via is self-aligned along the first direction to one of the second metallization lines, the second direction crossing the first direction at an angle.
1. A method of forming an electronic device, the method comprising:
forming a first metallization line, the first metallization line having a first width;
forming an oversized via mask on a via metallization layer on the first metallization line, the oversized via mask having a mask width and a mask length, the via mask comprising an extreme ultraviolet (EUV) trilayer on a hard mask layer and the mask width greater than the first width of the first metallization line;
forming a via, the via having a via metal length that is equal to the mask width and having a via metal width that is equal to the first width; and
forming a second metallization line.
2. The method of claim 1 , wherein forming the first metallization line comprises patterning the via metallization layer on a first metallization layer on an insulating layer on a substrate, the via metallization layer having a hard mask on a top surface.
3. The method of claim 2 , further comprising depositing a gapfill layer on the first metallization line.
4. The method of claim 3 , wherein the oversized via mask is formed on a top surface of the via metallization layer and on a top surface of the gapfill layer.
5. The method of claim 4 , wherein the via metallization layer and the first metallization layer are separated by an etch stop layer, and wherein the via metallization layer and the first metallization layer independently comprise one or more of copper (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), titanium (Ti), aluminum (Al), hafnium (Hf), tantalum (Ta), tungsten (W), vanadium (V), molybdenum (Mo), palladium (Pd), gold (Au), silver (Ag), platinum (Pt), indium (In), tin (Sn), lead (Pb), antimony (Sb), bismuth (Bi), zinc (Zn), or cadmium (Cd).
6. The method of claim 5 , wherein forming the via comprises:
etching the EUV trilayer to expose a top surface of the hard mask layer;
etching the hard mask layer to expose the via metallization layer;
etching the via metallization layer to expose the etch stop layer; and
removing the etch stop layer to expose a top surface of the first metallization layer.
7. The method of claim 6 , wherein the etch stop layer and the hard mask layer independently comprise one or more of titanium nitride (TiN), titanium (Ti), tantalum (Ta), or tantalum nitride (TaN), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), silicon nitride (SiN), silicon carbonitride (SiCN), tungsten carbide (WC), tungsten boron carbide (WBC), silicon boride (SiBx), boron carbide (BC), amorphous carbon, boron nitride (BN), boron carbon nitride (BCN), and the like.
8. The method of claim 2 , wherein the insulating layer comprises one or more oxides, carbon doped oxides, porous silicon dioxide, carbides, oxycarbides, nitrides, oxynitrides, oxycarbonitrides, polymers, phosphosilicate glass, fluorosilicate (SiOF) glass, organosilicate glass (SiOCH), or any combinations thereof.
9. A processor-implemented method for forming fully self-aligned vias, the method comprising:
receiving data for a first configuration to control forming a first metallization line, the first metallization line having a first width;
receiving data for a second configuration to control forming an oversized via mask on a via metallization layer on the first metallization line, the oversized via mask comprising an extreme ultraviolet (EUV) trilayer on a hard mask layer, the via mask having a mask width and a mask length and the mask width greater than the first width of the first metallization line;
receiving data for a third configuration to control forming a via, the via having a via metal length that is equal to the mask width and having a via metal width that is equal to the first width; and
receiving data for a fourth configuration to control forming a second metallization line.
10. The processor-implemented method of claim 9 , wherein forming the first metallization line comprises patterning a via metallization layer on a first metallization layer on an insulating layer on a substrate, the via metallization layer having a hard mask on a top surface, and the insulating layer comprising one or more of oxides, carbon doped oxides, porous silicon dioxide, carbides, oxycarbides, nitrides, oxynitrides, oxycarbonitrides, polymers, phosphosilicate glass, fluorosilicate (SiOF) glass, organosilicate glass (SiOCH), or any combinations thereof.
11. The processor-implemented method of claim 10 , further comprising receiving data for a fifth configuration to control depositing a gapfill layer on the first metallization line.
12. The processor-implemented method of claim 11 , wherein the oversized via mask is formed on the first metallization line and on the gapfill layer.
13. The processor-implemented method of claim 12 , wherein the via metallization layer and the first metallization layer are separated by an etch stop layer, the etch stop layer and the hard mask layer independently comprising one or more of titanium nitride (TiN), titanium (Ti), tantalum (Ta), or tantalum nitride (TaN), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), silicon nitride (SiN), or silicon carbonitride (SiCN), and wherein the via metallization layer and the first metallization layer independently comprise one or more of copper (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), titanium (Ti), aluminum (Al), hafnium (Hf), tantalum (Ta), tungsten (W), vanadium (V), molybdenum (Mo), palladium (Pd), gold (Au), silver (Ag), platinum (Pt), indium (In), tin (Sn), lead (Pb), antimony (Sb), bismuth (Bi), zinc (Zn), or cadmium (Cd).
14. The processor-implemented method of claim 13 , wherein forming the via comprises:
etching the EUV trilayer to expose a top surface of the hard mask layer;
etching the hard mask layer to expose the via metallization layer;
etching the via metallization layer to expose the etch stop layer; and
removing the etch stop layer to expose a top surface of the first metallization layer.