Method and apparatus for low power chip-to-chip communications with constrained ISI ratio
An efficient communications apparatus is described for a vector signaling code to transport data and optionally a clocking signal between integrated circuit devices. Methods of designing such apparatus and their associated codes based on a new metric herein called the “ISI Ratio” are described which permit higher communications speed, lower system power consumption, and reduced implementation complexity.
1. A method comprising:
obtaining, from a data source, a set of signals representing information for transmission over a multi-wire bus according to an orthogonal differential vector signaling (ODVS) code, the ODVS code having an encoding matrix composed of a plurality of mutually-orthogonal sub-channel vector rows, each sub-channel vector row associated with a respective signal of the set of signals;
generating a set of output signals corresponding to symbols of a codeword of the ODVS code, wherein each symbol of the codeword has a symbol value selected from a set of at least four symbol values and represents a weighted sum of sub-channel vector elements in a respective column of the encoding matrix, each sub-channel vector element weighted by a respective signal of the set of signals, wherein the weighted sum of sub-channel vector elements for a first symbol comprises a different number of sub-channel vector elements than the weighted sum of sub-channel vector elements for a second symbol; and
transmitting each output signal as an analog signal on a respective wire of the multi-wire bus.
2. The method of claim 1 , wherein each signal of the set of signals is a pulse-amplitude modulated (PAM)-2 signal.
3. The method of claim 1 , wherein each signal of the set of signals is a pulse-amplitude modulated (PAM)-X signal, where X is an integer greater than 2.
4. The method of claim 1 , wherein the encoding matrix comprises sub-channel code vector rows having three non-zero sub-channel vector elements comprising a first non-zero sub-channel vector element twice as large as each of a second non-zero sub-channel vector element and a third non-zero sub-channel vector element, and a position of the first non-zero sub-channel vector element is aligned to where only one other sub-channel vector row has a non-zero sub-channel vector element.
5. The method of claim 4 , wherein for an input vector S=[0, S 0 , S 1 , S 2 , S 3 , S 4 ] containing the set of signals, the encoding matrix corresponds to:
A
=
[
1
1
1
1
1
1
1
-
1
0
0
0
0
1
1
-
2
0
0
0
0
0
0
1
-
1
0
0
0
0
1
1
-
2
1
1
1
-
1
-
1
-
1
]
and the set of output signals correspond to S·A.
6. The method of claim 1 , wherein a sum of the symbols of the codeword is equal to zero.
7. The method of claim 1 , wherein each sub-channel vector element is further weighted by a respective scaling factor of a set of scaling factors.
8. The method of claim 7 , wherein the set of scaling factors are associated with an ODVS code comprising reduced-alphabet codewords.
9. The method of claim 7 , wherein the set of scaling factors are associated with normalized gain across the plurality of sub-channel vector rows.
10. An apparatus comprising:
an orthogonal differential vector signaling (ODVS) encoder configured to:
obtain, from a data source, a set of signals representing information for transmission over a multi-wire bus according to an orthogonal differential vector signaling (ODVS) code, the ODVS code having an encoding matrix composed of a plurality of mutually-orthogonal sub-channel vector rows, each sub-channel vector row associated with a respective signal of the set of signals; and
generate a set of output signals corresponding to symbols of a codeword of the ODVS code, wherein each symbol of the codeword has a symbol value selected from a set of at least four symbol values and represents a weighted sum of sub-channel vector elements in a respective column of the encoding matrix, each sub-channel vector element weighted by a respective signal of the set of signals, wherein the weighted sum of sub-channel vector elements for a first symbol comprises a different number of sub-channel vector elements than the weighted sum of sub-channel vector elements for a second symbol; and
a set of output drivers configured to generate each output signal as an analog signal on a respective wire of the multi-wire bus.
11. The apparatus of claim 10 , wherein each signal of the set of signals is a pulse-amplitude modulated (PAM)- 2 signal.
12. The apparatus of claim 10 , wherein each signal of the set of signals is a pulse-amplitude modulated (PAM)-X signal, where X is an integer greater than 2.
13. The apparatus of claim 10 , wherein the encoding matrix comprises sub-channel code vector rows having three non-zero sub-channel vector elements comprising a first non-zero sub-channel vector element twice as large as each of a second non-zero sub-channel vector element and a third non-zero sub-channel vector element, and a position of the first non-zero sub-channel vector element is aligned to where only one other sub-channel vector row has a non-zero sub-channel vector element.
14. The apparatus of claim 13 , wherein for an input vector S=[0, S 0 , S 1 , S 2 , S 3 , S 4 ] containing the set of signals, the encoding matrix corresponds to:
A
=
[
1
1
1
1
1
1
1
-
1
0
0
0
0
1
1
-
2
0
0
0
0
0
0
1
-
1
0
0
0
0
1
1
-
2
1
1
1
-
1
-
1
-
1
]
and the set of output signals correspond to S·A.
15. The apparatus of claim 10 , wherein a sum of the symbols of the codeword is equal to zero.
16. The apparatus of claim 10 , wherein each sub-channel vector element is further weighted by a respective scaling factor of a set of scaling factors.
17. The apparatus of claim 16 , wherein the set of scaling factors are associated with an ODVS code comprising reduced-alphabet codewords.
18. The apparatus of claim 16 , wherein the set of scaling factors are associated with normalized gain across the plurality of sub-channel vector rows.