FeFET with double gate structure
An approach for representing both positive and negative weights in neuromorphic computing is disclosed. The approach leverages a double gate FeFET (ferroelectric field effect transistor) device. The device leverages a double-gate FeFET with four terminals (two separate gates and source and drain) and ferroelectric gate dielectric. The device may have a junction-less channel. A synaptic weight is programmed by biasing one of the two gates. The store weight is sensed via a current flow from source to drain. A pre-defined bias is applied to the other gate during the sensing, such that a reference current is subtracted from the drain current. The net current for sensing is current from the synaptic devices subtracted by the pre-defined reference current.
1. A device for computing, the device comprising:
one or more gate stacks are disposed on a fin semiconductor device;
a first gate stack of the one or more gate stacks comprises of a first ferroelectric layer and first interfacial layer, respectively;
a second gate stack of the one or more gate stacks comprises of a second ferroelectric layer and second interfacial layer, respectively and wherein the second ferroelectric layer contains a higher concentration of defects than the first ferroelectric layer which contributes to a leakage current, wherein the leakage current flows from the first gate stack towards the second gate stack;
the first gate stack of the one or more gate stacks contains a first gate and the second gate stack of the one or more gate stacks contains a second gate;
a fin is disposed between the second interfacial layer and the first interfacial layer, wherein the fin consists of a junction-less channel and the fin consists of one or more depletion layers; and
a source terminal and a drain terminal formed on either ends of the fin, wherein a drain current flows from the source terminal towards the drain terminal.
2. The device of claim 1 , wherein the semiconductor device comprises of nanosheet, planar and FET structures.
3. The device of claim 1 , wherein the defects consists of oxygen vacancies.
4. The device of claim 1 , wherein the first ferroelectric layer act as a dielectric for the first gate.
5. The device of claim 1 , wherein the second ferroelectric layer act as a dielectric for the second gate.
6. The device of claim 1 , wherein the first interfacial layer has a different thickness than the second interfacial layer by 0.5 nm to 1.0 nm.
7. The device of claim 1 , wherein one or more channels is doped with either n-type or p-type and wherein concentration of doping is 1E19 cm −3 or higher.
8. The device of claim 1 , wherein thickness of the first ferroelectric layer and the second ferroelectric layer is between 2 to 10 nm.
9. The device of claim 6 , wherein the first and second interfacial layers, respectively, has a thickness range between 0.5 nm to 1.5 nm and is composed of SiO 2 .