Nitride-containing STI liner for SiGe channel

1. A method for manufacturing a semiconductor structure, comprising:

forming a fin structure that protrudes vertically out of a substrate, wherein the fin structure includes a first segment and a second segment different from, and disposed below, the first segment;

epitaxially growing a silicon layer on surfaces of the fin structure, wherein a first portion of the silicon layer grown on the first segment is thicker than a second portion of the silicon layer grown on the second segment;

performing a first rapid thermal nitridation (RTN) process, wherein the first RTN process implants nitrogen into the epitaxially grown silicon layer;

forming a dielectric liner layer over the epitaxially grown silicon layer after the first RTN process has been performed; and

forming a dielectric isolation structure over the dielectric liner layer.

2. The method of claim 1 , wherein:

the forming the fin structure includes performing one or more etching processes to pattern the fin structure, wherein the fin structure has a first surface roughness after the performing the one or more etching processes; and

the silicon layer that is epitaxially grown on the fin structure has a second surface roughness that is less than the first surface roughness.

3. The method of claim 1 , wherein the forming the fin structure includes forming a P-type fin structure that includes a silicon germanium material.

4. The method of claim 3 , wherein:

the first segment of the fin structure includes one or more mask layers, and wherein the second segment of the fin structure includes the silicon germanium material;

the first portion of the silicon layer is epitaxially grown on the one or more mask layers; and

the second portion of the silicon layer is epitaxially grown on the silicon germanium material.

5. The method of claim 1 , further including:

forming a silicon oxide liner on the silicon layer after the first RTN process has been performed; and

forming an isolation structure over the silicon oxide liner.

6. The method of claim 1 , wherein:

the forming the dielectric liner layer further includes forming a silicon oxide liner layer on the epitaxially grown silicon layer; and

the forming the dielectric isolation structure includes forming a shallow trench isolation (STI) structure directly on the silicon oxide liner layer.

7. The method of claim 1 , wherein:

the forming the dielectric liner layer further includes forming a silicon nitride liner layer on the epitaxially grown silicon layer; and

the forming the dielectric isolation structure includes forming a shallow trench isolation (STI) structure directly on the silicon nitride liner layer.

8. The method of claim 1 , wherein:

the forming the dielectric liner layer further includes forming a silicon oxide liner layer on the epitaxially grown silicon layer;

the method further includes performing a second RTN process to implant nitrogen into the silicon oxide liner layer; and

the forming the dielectric isolation structure includes forming a shallow trench isolation (STI) structure directly on the silicon oxide liner layer.

9. The method of claim 1 , wherein:

the forming the dielectric liner layer further includes forming a silicon oxide liner layer on the epitaxially grown silicon layer;

the method further includes:

performing a second RTN process to implant nitrogen into the silicon oxide liner layer; and

forming a silicon nitride liner layer directly on the silicon oxide liner layer; and

the forming the dielectric isolation structure includes forming a shallow trench isolation (STI) structure directly on the silicon nitride liner layer.

10. The method of claim 9 , wherein:

the silicon oxide liner layer is formed to have a first thickness;

the silicon nitride liner layer is formed to have a second thickness; and

the first thickness is greater than the second thickness.

11. A method for manufacturing a semiconductor structure, comprising:

patterning a silicon germanium material into a p-type fin structure, wherein the patterning includes one or more etching processes performed while using a mask structure formed over the silicon germanium material;

growing a first portion of an epi-layer on the patterned silicon germanium material and growing a second portion of the epi-layer over the mask structure, wherein the first portion of the epi-layer is grown to be thinner than the second portion of the epi-layer, and wherein the second portion of the epi-layer is located above the first portion of the epi-layer;

implanting nitrogen into the epi-layer;

depositing a silicon oxide liner layer on the epi-layer after nitrogen has been implanted into the epi-layer;

implanting nitrogen into the silicon oxide liner layer; and

forming a shallow trench isolation (STI) structure over the silicon oxide liner layer after nitrogen has been implanted into the silicon oxide liner layer.

12. The method of claim 11 , further including, after the implanting the nitrogen into the silicon oxide liner layer but before the forming of the STI structure, depositing a silicon nitride liner layer on the silicon oxide liner layer, wherein the STI structure is formed over the silicon nitride liner layer.

13. The method of claim 12 , wherein the silicon nitride liner layer is formed to be thinner than the silicon oxide liner layer.

14. The method of claim 11 , wherein:

the implanting the nitrogen into the epi-layer includes performing a first thermal nitridation process; and

the implanting the nitrogen into the silicon oxide liner layer includes performing a second thermal nitridation process.

15. The method of claim 11 , wherein the depositing a silicon oxide liner layer is performed using a plasma enhanced oxidation process.

16. A method for manufacturing a semiconductor structure, comprising:

forming a silicon layer over a first P-type fin structure and over a second P-type fin structure that each protrude vertically out of a substrate, wherein first portions of the silicon layer formed over upper segments of the first P-type fin structure and the second P-type fin structure are thicker than second portions of the silicon layer formed over lower segments of the first P-type fin structure and the second P-type fin structure;

introducing nitrogen into the silicon layer;

after the nitrogen has been introduced to the silicon layer, forming a dielectric layer over the silicon layer; and

forming a dielectric isolation structure between the first P-type fin structure and the second P-type fin structure, wherein the dielectric isolation structure is formed over the dielectric layer.

17. The method of claim 16 , wherein a surface of the silicon layer is smoother than a surface of the first P-type fin structure or a surface of the second P-type fin structure.

18. The method of claim 16 , wherein the nitrogen is implanted into the silicon layer via a nitridation process having a process temperature in a range between about 600 degrees Celsius and about 800 degrees Celsius and a process duration in a range between about 30 seconds and about 180 seconds.

19. The method of claim 16 , wherein the dielectric layer is formed in a processing chamber where hydrogen and oxygen are introduced, and wherein a temperature of the substrate is sufficiently high to initiate a conversion of the hydrogen and the oxygen into water.

20. The method of claim 16 , wherein the forming the silicon layer is performed such that the silicon layer contains both crystal silicon and amorphous silicon.