Transistor source/drain contacts and methods of forming the same

1. A method comprising:

depositing a protective layer on a source/drain region and a gate mask, the gate mask disposed on a gate structure, the gate structure disposed on a channel region of a substrate, the channel region adjoining the source/drain region;

etching an opening through the protective layer, the opening exposing the source/drain region;

depositing a metal in the opening and on the protective layer;

annealing the metal to form a metal-semiconductor alloy region on the source/drain region; and

removing residue of the metal from the opening with a cleaning process, the protective layer covering the gate mask during the cleaning process.

2. The method of claim 1 , wherein the cleaning process comprises performing a wet etch using dilute hydrofluoric acid, and no etching of the gate mask occurs during the wet etch.

3. The method of claim 1 , wherein the source/drain region comprises a main layer and a finishing layer, the method further comprising:

etching the opening through the finishing layer of the source/drain region, the opening exposing the main layer of the source/drain region.

4. The method of claim 3 , wherein the protective layer comprises silicon nitride, and etching the opening comprises performing a dry etch using carbonyl sulfide.

5. The method of claim 4 , wherein no etching of the main layer of the source/drain region occurs during the dry etch.

6. The method of claim 1 , wherein the protective layer has a thickness in a range of 1 nm to 3 nm.

7. The method of claim 1 further comprising:

depositing a contact etch stop layer (CESL) on the source/drain region;

forming an inter-layer dielectric (ILD) on the CESL;

forming a contact opening through the ILD and the CESL; and

after forming the contact opening, expanding the contact opening, the protective layer deposited in the contact opening after expanding the contact opening.

8. The method of claim 7 , wherein expanding the contact opening comprises etching the ILD with hydrogen fluoride and ammonia at room temperature.

9. A method comprising:

depositing a contact etch stop layer (CESL) on a source/drain region;

forming an inter-layer dielectric (ILD) on the CESL;

forming a contact opening through the ILD and the CESL, the contact opening exposing a top surface of the source/drain region and a sidewall of the CESL;

after forming the contact opening, expanding the contact opening by etching the ILD with an isotropic etching process that selectively etches a material of the ILD at a faster rate than a material of the source/drain region; and

forming a source/drain contact in the contact opening.

10. The method of claim 9 , wherein the isotropic etching process comprises:

performing a dry etch with an etching gas solution in the contact opening, the dry etch performed without plasma, the etching gas solution converting the ILD to a solid phase byproduct;

performing a thermal treatment to sublimate the solid phase byproduct to a gas phase byproduct; and

evacuating the gas phase byproduct from the contact opening.

11. The method of claim 10 , wherein the etching gas solution comprises hydrogen fluoride and ammonia, and the dry etch is performed at room temperature.

12. The method of claim 10 , wherein the etching gas solution comprises hydrogen fluoride, and the dry etch is performed at a temperature in a range of 20° C. to 40° C.

13. The method of claim 10 , wherein the dry etch is performed at a first temperature, and the thermal treatment is performed at a second temperature, the second temperature greater than the first temperature.

14. The method of claim 10 , wherein the ILD comprises silicon oxide, and the solid phase byproduct comprises ammonium fluorosilicate.

15. The method of claim 9 further comprising:

forming a gate structure on a channel region of a substrate, the channel region adjoining the source/drain region;

forming a gate mask on the gate structure;

after expanding the contact opening, depositing a protective layer on the gate mask and in the contact opening;

extending the contact opening through the protective layer; and

forming a metal-semiconductor alloy region in the contact opening while the protective layer covers the gate mask.

16. The method of claim 15 , wherein forming the metal-semiconductor alloy region comprises performing a cleaning process, and no etching of the gate mask occurs during the cleaning process.

17. The method of claim 15 , wherein extending the contact opening through the protective layer comprises etching the contact opening with carbonyl sulfide.

18. A method comprising:

forming a contact opening through an inter-layer dielectric, the contact opening exposing a top surface of a source/drain region;

after forming the contact opening, expanding the contact opening by etching the inter-layer dielectric with an isotropic etching process;

after expanding the contact opening, depositing a protective layer in the contact opening and on a gate mask, the gate mask adjacent the source/drain region;

extending the contact opening through the protective layer; and

forming a metal-semiconductor alloy region in the contact opening while the protective layer covers the gate mask.

19. The method of claim 18 , wherein the isotropic etching process comprises:

performing a dry etch with an etching gas solution in the contact opening, the dry etch performed without plasma, the etching gas solution converting the inter-layer dielectric to a solid phase byproduct;

performing a thermal treatment to sublimate the solid phase byproduct to a gas phase byproduct; and

evacuating the gas phase byproduct from the contact opening.

20. The method of claim 18 , wherein the protective layer comprises silicon nitride, and extending the contact opening through the protective layer comprises performing a dry etch using carbonyl sulfide.