Soft read operations with progressive data output
Systems, apparatuses and methods may provide for memory controller technology including first logic to trigger, via an initial request, a hard-read and a soft-read, wherein the hard-read is to generate hard-bit information and the soft-read is to generate first soft-bit information and second soft-bit information, conduct a first error correction on the hard-bit information, and issue a subsequent request for at least the second soft-bit information if the first error correction is unsuccessful. Additionally, memory device technology may include a plurality of memory cells and second logic to conduct the hard-read and the soft-read from a memory cell in the plurality of memory cells in response to the initial request, send the hard-bit information to the controller, and withhold at least the second soft-bit information from the controller until the subsequent request is received.
1. A memory device comprising:
a plurality of memory cells; and
logic coupled to one or more substrates, the logic to:
conduct a hard-read and a soft-read from a memory cell in the plurality of memory cells in response to an initial request from a controller, wherein the hard-read is to generate hard-bit information and the soft-read is to generate first soft-bit information and second soft-bit information;
send the hard-bit information to the controller;
send the first soft-bit information with the hard-bit information to the controller while withholding at least the second soft-bit information from the controller;
detect a subsequent request from the controller; and
send the second soft-bit information to the controller in response to the subsequent request.
2. The memory device of claim 1 , wherein the soft-read is to be one or more of a 5-strobe soft-read or a 7-strobe soft-read.
3. The memory device of claim 1 , wherein the logic is further to store at least the second soft-bit information locally on the memory device while the hard-bit information is being processed by the controller.
4. The memory device of claim 1 , wherein the hard-bit information is to be sent to the controller via a shared bus.
5. The memory device of claim 1 , wherein to conduct the hard-read and the soft-read, the logic is further to:
maintain a voltage of a wordline associated with the memory cell at a read voltage level; and
compare a current of a bitline associated with the memory cell to a plurality of reference current levels.
6. A memory chip controller comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
trigger, via an initial request, a hard-read and a soft-read with respect to a memory cell in a memory device, wherein the hard-read is to generate hard-bit information and the soft-read is to generate first soft-bit information and second soft-bit information;
conduct a first error correction on the hard-bit information; and
issue a subsequent request for at least the second soft-bit information if the first error correction is unsuccessful.
7. The memory chip controller of claim 6 , wherein the logic coupled to the one or more substrates is further to conduct a second error correction on the hard-bit information, the first soft-bit information, and the second soft-bit information.
8. The memory chip controller of claim 7 , wherein the logic coupled to the one or more substrates is further to obtain the hard-bit information, the first soft-bit information, and the second soft-bit information from a shared bus.
9. The memory chip controller of claim 6 , wherein the logic coupled to the one or more substrates is further to exclude the second soft-bit information from the first error correction.
10. The memory chip controller of claim 6 , wherein the first error correction is conducted further on the first soft-bit information.
11. The memory chip controller of claim 6 , wherein the soft-read is to be one or more of a 5-strobe soft-read or a 7-strobe soft-read.
12. The memory chip controller of claim 6 , wherein the logic coupled to the one or more substrates is to store the hard-bit information locally on the controller until at least the second soft-bit information is received from the memory device.
13. A computing system comprising:
a memory chip controller including first logic to:
trigger, via an initial request, a hard-read and a soft-read, wherein the hard-read is to generate hard-bit information and the soft-read is to generate first soft-bit information and second soft-bit information,
conduct a first error correction on the hard-bit information, and
issue a subsequent request for at least the second soft-bit information if the first error correction is unsuccessful; and
a memory device including a plurality of memory cells and second logic to:
conduct the hard-read and the soft-read from a memory cell in the plurality of memory cells in response to the initial request,
send the hard-bit information to the controller; and
withhold at least the second soft-bit information from the controller until the subsequent request is received.
14. The computing system of claim 13 , wherein the first logic is to conduct a second error correction on the hard-bit information, the first soft-bit information, and the second soft-bit information.
15. The computing system of claim 13 , wherein the first logic is to obtain the hard-bit information, the first soft-bit information, and the second soft-bit information from a shared bus.
16. The computing system of claim 13 , wherein the first error correction is conducted further on the first soft-bit information.
17. The computing system of claim 13 , wherein to conduct the hard-read and the soft-read, the second logic is further to:
maintain a voltage of a wordline associated with the memory cell at a read voltage level, and
compare a current of a bitline associated with the memory cell to a plurality of reference current levels.
18. The computing system of claim 13 , wherein the soft-read is to be one or more of a 5-strobe soft-read or a 7-strobe soft-read.