System and method for fast and accurate netlist to RTL reverse engineering
Embodiments herein provide for reverse engineering of integrated circuits (ICs) for design verification. In example embodiments, an apparatus receives a gate-level netlist for an integrated circuit (IC), generates a list of equivalence classes related to signals included in the gate-level netlist, determines control signals of the gate-level netlist based at least in part on the list of equivalence classes, determines a logic flow of a finite state transducer (FST) based at least in part on the control signals, and generates register transfer level (RTL) source code for the IC based on the FST.
1. A method for reverse engineering of integrated circuits (ICs) for design verification, the method comprising:
receiving a gate-level netlist for an integrated circuit (IC), wherein the gate-level netlist comprises a description of connectivity for the integrated circuit and is formatted in a hardware description language;
generating, based at least in part on signals included in the gate-level netlist, a list of equivalence classes related to the signals;
determining, based at least in part on the list of equivalence classes, control signals of the gate-level netlist;
determining, based at least in part on the control signals, a logic flow of a finite state transducer (FST); and
generating, based at least in part on the FST, register transfer level (RTL) source code for the IC, wherein the RTL source code models the IC based on one or more of flow of signals between hardware components of the IC or logical operations associated with the signals.
2. The method of claim 1 , further comprising:
extracting the control signals from the gate-level netlist of design using truth table equivalence classes.
3. The method of claim 2 , further comprising:
comparing the truth table equivalence classes for uniqueness.
4. The method of claim 2 , further comprising:
presenting signals for the truth table equivalence classes as the control signals.
5. The method of claim 1 , wherein the generating the RTL source code comprises generating the RTL source code via Finite State Transducer (FST) extraction.
6. The method of claim 5 , further comprising:
identifying output signals of the FST using dominator trees.
7. An apparatus comprising at least one processor and at least one non-transitory storage medium storing instructions that, with the at least one processor, cause the apparatus to:
receive a gate-level netlist for an integrated circuit (IC), wherein the gate-level netlist comprises a description of connectivity for the integrated circuit and is formatted in a hardware description language;
generate, based at least in part on signals included in the gate-level netlist, a list of equivalence classes related to the signals;
determine, based at least in part on the list of equivalence classes, control signals of the gate-level netlist;
determine, based at least in part on the control signals, a logic flow of a finite state transducer (FST); and
generate, based at least in part on the FST, register transfer level (RTL) source code for the IC, wherein the RTL source code models the IC based on one or more of flow of signals between hardware components of the IC or logical operations associated with the signals.
8. The apparatus of claim 7 , wherein the at least one non-transitory storage medium stores instructions that, with the at least one processor, further cause the apparatus to:
extract the control signals from the gate-level netlist of design using truth table equivalence classes.
9. The apparatus of claim 8 , wherein the at least one non-transitory storage medium stores instructions that, with the at least one processor, further cause the apparatus to:
compare the truth table equivalence classes for uniqueness.
10. The apparatus of claim 8 , wherein the at least one non-transitory storage medium stores instructions that, with the at least one processor, further cause the apparatus to:
present signals for the truth table equivalence classes as the control signals.
11. The apparatus of claim 7 , wherein the generating the RTL source code comprises generating the RTL source code via Finite State Transducer (FST) extraction.
12. The apparatus of claim 11 , wherein the at least one non-transitory storage medium stores instructions that, with the at least one processor, further cause the apparatus to:
identify output signals of the FST using dominator trees.
13. A computer program product comprising at least one non-transitory computer-readable storage medium storing instructions that, when executed by at least one processor, cause an apparatus to:
receive a gate-level netlist for an integrated circuit (IC), wherein the gate-level netlist comprises a description of connectivity for the integrated circuit and is formatted in a hardware description language;
generate, based at least in part on signals included in the gate-level netlist, a list of equivalence classes related to the signals;
determine, based at least in part on the list of equivalence classes, control signals of the gate-level netlist;
determine, based at least in part on the control signals, a logic flow of a finite state transducer (FST); and
generate, based at least in part on the FST, register transfer level (RTL) source code for the IC, wherein the RTL source code models the IC based on one or more of flow of signals between hardware components of the IC or logical operations associated with the signals.
14. The computer program product of claim 13 , wherein the at least one non-transitory computer-readable storage medium stores instructions that, with the at least one processor, further cause the apparatus to:
extract the control signals from the gate-level netlist of design using truth table equivalence classes.
15. The computer program product of claim 14 , wherein the at least one non-transitory computer-readable storage medium stores instructions that, with the at least one processor, further cause the apparatus to:
compare the truth table equivalence classes for uniqueness.
16. The computer program product of claim 14 , wherein the at least one non-transitory computer-readable storage medium stores instructions that, with the at least one processor, further cause the apparatus to:
present signals for the truth table equivalence classes as the control signals.
17. The computer program product of claim 13 , wherein the generating the RTL source code comprises generating the RTL source code via Finite State Transducer (FST) extraction.
18. The computer program product of claim 17 , wherein the at least one non-transitory computer-readable storage medium stores instructions that, with the at least one processor, further cause the apparatus to:
identify output signals of the FST using dominator trees.