Signal drop compensated memory

1. An apparatus, comprising:

a memory array comprising memory cells;

sensing circuitry coupled to the memory array and configured to:

apply a first signal to a terminal of a particular transistor;

mirror the first signal to a decoder replica;

apply a second signal to a gate of the particular transistor, the second signal comprising a sensing signal and a signal drop on the decoder replica; and

sense a state of the particular transistor.

2. The apparatus of claim 1 , wherein the decoder replica replicates a decoder of the sensing circuitry, and wherein the decoder replica is part of a current feedback loop.

3. The apparatus of claim 2 , wherein the current feedback loop has a positive gain.

4. The apparatus of claim 3 , wherein the sensing circuitry is configured to bleed an output of a second terminal of the particular transistor to stabilize a sense line coupled to the second terminal.

5. The apparatus of claim 4 , wherein the sensing circuitry is configured to bleed the mirrored first signal analogously to the output of the second terminal.

6. An apparatus, comprising:

a memory array comprising memory cells;

sensing circuitry coupled to the memory array and comprising:

a decoder coupled to the memory array;

a decoder replica, which replicates the decoder, coupled to the memory array; and

a current mirror coupled to the decoder replica and to the memory array, wherein the current mirror is configured to provide a signal to a terminal of a selected transistor and a mirrored signal to the decoder replica;

wherein the decoder replica is configured to provide a signal drop of the decoder replica to a gate of the selected transistor responsive to the mirrored signal being applied to the decoder replica, wherein the signal drop replicates a corresponding signal drop of the decoder;

wherein the sensing circuitry is configured to:

provide a sensing signal to the gate of the selected transistor simultaneously with the signal drop provided by the decoder replica; and

sense a state of the selected transistor.

7. The apparatus of claim 6 , wherein the current mirror comprises a capacitor; and

wherein the sensing circuitry comprises precharge circuitry coupled to a sense line via the selected transistor and to the capacitor;

wherein the precharge circuitry is configured to simultaneously precharge the sense line and the capacitor.

8. The apparatus of claim 7 , wherein the sensing circuitry comprises a switch coupled between the capacitor and the precharge circuitry; and

wherein the sensing circuitry is configured to close the switch to precharge the capacitor.

9. The apparatus of claim 8 , wherein the current mirror further comprises:

a first transistor coupled to the capacitor via a gate of the first transistor and configured to provide the signal to the selected transistor; and

a second transistor coupled to the capacitor via a gate of the second transistor and configured to provide the mirrored signal to the decoder replica.

10. The apparatus of claim 9 , wherein the sensing circuitry is configured to precharge the capacitor by:

providing a precharge signal to a third transistor, and

wherein the third transistor is configured to provide the precharge signal to the selected transistor and the switch coupling the capacitor to the third transistor.

11. The apparatus of claim 10 , wherein the sensing circuitry is configured to precharge the capacitor by closing the switch to provide the precharge signal to the capacitor.

12. The apparatus of claim 9 , wherein the sensing circuitry is configured to calibrate the selected transistor by:

configuring the third transistor to refrain from providing the precharge signal to the selected transistor and the switch coupling the capacitor to the third transistor, wherein the switch is closed.

13. The apparatus of claim 9 , wherein the capacitor is configured to:

provide an activation signal to the gate of the first transistor to cause the first transistor to provide the signal to the selected transistor; and

provide the activation signal to the gate of the second transistor to cause the second transistor to provide the mirrored signal to the decoder replica.

14. The apparatus of claim 9 , wherein the sensing circuitry is configured to hold the signal by:

configuring the third transistor to refrain from providing the precharge signal to the selected transistor and the switch coupling the capacitor to the third transistor and wherein the switch is open; and

wherein the capacitor is configured to:

provide the activation signal to the gate of the first transistor to cause the first transistor to provide the signal to the selected transistor; and

provide the activation signal to the gate of the second transistor to cause the second transistor to provide the mirrored signal to the decoder replica.

15. The apparatus of claim 9 , wherein the sensing circuitry is configured to:

configure the third transistor to refrain from providing the precharge signal to the selected transistor and the switch coupling the capacitor to the third transistor, wherein the switch is open; and

wherein the capacitor is configured to:

provide the activation signal to the gate of the first transistor to cause the first transistor to provide the signal to the selected transistor; and

provide the activation signal to the gate of the second transistor to cause the second transistor to provide the mirrored signal to the decoder replica; and

configure a fourth transistor to provide a reference signal to the terminal of the selected transistor simultaneously with the signal.

16. The apparatus of claim 9 , wherein the sensing circuitry is configured to sense the selected transistor by:

configuring the third transistor to refrain from providing the precharge signal to the selected transistor and the switch coupling the capacitor to the third transistor, wherein the switch is open; and

wherein the capacitor is configured to:

provide the activation signal to the gate of the first transistor to cause the first transistor to provide the signal to the selected transistor;

provide the activation signal to the gate of the second transistor to cause the second transistor to provide the signal to the decoder replica;

wherein the decoder replica is configured to provide the signal drop to the gate of the selected transistor, wherein the signal drop is provided simultaneously with the sensing signal; and

wherein the sensing circuitry further comprises a snap detector configured to:

receive a detector activation signal; and

responsive to receipt of the detector activation signal, detect a state of the selected transistor.

17. A method, comprising:

providing, from a memory array of memory cells of a memory device, a signal to a terminal of a selected transistor of sensing circuitry;

providing, from a current mirror, a mirrored signal to the terminal of the selected transistor and a decoder replica subsequent to providing the signal, wherein the mirrored signal corresponds to the signal;

generating a signal drop of the decoder replica responsive to the mirrored signal being applied to the decoder replica, wherein the signal drop replicates a corresponding signal drop of a decoder;

determining whether the signal drop is greater than a threshold; and

responsive to determining that the signal drop is greater than the threshold, setting a register of a controller of the memory device to identify a plurality of actions that are to be performed on an output of the decoder comprising the selected transistor.

18. The method of claim 17 , further comprising setting the register of the controller of the memory device to cause a plurality of error correction code (ECC) operations to be performed on the output of the decoder.

19. The method of claim 18 , wherein setting the register further comprises storing an address corresponding to the signal and wherein the ECC operations are performed on signals originating from memory cells having the address.

20. The method of claim 18 , wherein the ECC operations include error erasure operations.

21. The method of claim 17 , further comprising, responsive to setting the register, performing the plurality of actions during a media maintenance cycle of the memory array.