IP Library › Granted Patent US 11,705,364
Granted Patent B2
US 11,705,364 · App. 17/343,360 · Granted Jul 18, 2023

Method for preparing semiconductor device with air gap

Inventor: Liang-Pin Chou (Taoyuan, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
H01L21/7682H01L21/76837H01L21/76877H01L23/528H01L23/5329H10B12/315H10B12/482H10B12/485H10B12/34
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Quick Facts
Patent No.
US 11,705,364
App. No.
17/343,360
Granted
Jul 18, 2023
Kind
B2
Abstract

The present disclosure relates to a method for preparing a semiconductor device with air gaps between conductive lines (e.g., bit lines). The method includes forming a first dielectric structure and a second dielectric structure over a semiconductor substrate, and forming a conductive material over the first dielectric structure and the second dielectric structure. The conductive material extends into a first opening between the first dielectric structure and the second dielectric structure. The method also includes partially removing the conductive material to form a first bit line and a second bit line in the first opening and forming a sealing dielectric layer over the first bit line and the second bit line such that an air gap is formed between the sealing dielectric layer and the semiconductor substrate.

Claims (13)

1. A method for preparing a semiconductor device, comprising:

forming a first dielectric structure and a second dielectric structure over a semiconductor substrate;

forming a conductive material over the first dielectric structure and the second dielectric structure, wherein the conductive material extends into a first opening between the first dielectric structure and the second dielectric structure;

partially removing the conductive material to form a first bit line and a second bit line in the first opening; and

forming a sealing dielectric layer over the first bit line and the second bit line such that an air gap is formed between the sealing dielectric layer and the semiconductor substrate,

wherein a top surface of the semiconductor substrate between the first bit line and the second bit line is exposed after the partial removal of the conductive material.

2. The method for preparing a semiconductor device of claim 1 , wherein the first bit line is in direct contact with the first dielectric structure, and the second bit line is in direct contact with the second dielectric structure.

3. The method for preparing a semiconductor device of claim 1 , wherein the first bit line and the second bit line are separated by a second opening, and the sealing dielectric layer extends into a top portion of the second opening to form the air gap.

4. The method for preparing a semiconductor device of claim 1 , further comprising:

forming a first bit line contact and a second bit line contact in the semiconductor substrate, wherein the first bit line contact and the second bit line contact are between the first dielectric structure and the second dielectric structure.

5. The method for preparing a semiconductor device of claim 4 , wherein a portion of the conductive material between the first bit line contact and the second bit line contact is removed during the partial removal of the conductive material.

6. The method for preparing a semiconductor device of claim 4 , wherein a recess surrounded by the conductive material is formed before the conductive material is partially removed, and the recess is between the first bit line contact and the second bit line contact.

7. The method for preparing a semiconductor device of claim 6 , wherein a bottom surface of the recess is higher than a top surface of the semiconductor substrate.

Continuity (2)
Division 16561562 · Sep 5, 2019
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