IP Library › Granted Patent US 12,051,638
Granted Patent B2
US 12,051,638 · App. 17/344,231 · Granted Jul 30, 2024

Integrated high efficiency transistor cooling

Inventors: Daniel Chanemougame (Niskayuna, NY); Lars Liebmann (Mechanicsville, NY); Jeffrey Smith (Clifton Park, NY); Paul Gutwin (Williston, VT)
Assignee: Tokyo Electron Limited
H01L23/473H01L21/823481H01L21/823878H01L27/0886H01L27/092
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Quick Facts
Patent No.
US 12,051,638
App. No.
17/344,231
Granted
Jul 30, 2024
Kind
B2
Abstract

A microfabrication device is provided. The microfabrication device includes a transistor plane formed on a substrate, the transistor plane including a plurality of field effect transistors; fluidic passages formed within the transistor plane; a dielectric fluid added to the fluidic passages; and a circulating mechanism configured to circulate the dielectric fluid through the transistor plane.

Claims (14)

1. A microfabrication device comprising:

a transistor plane formed on a substrate, the transistor plane including a plurality of field effect transistors;

fluidic passages formed within the transistor plane, wherein the formation of the fluidic passages includes removing at least a portion of solid-state dielectric materials surrounding the plurality of field effect transistors;

a dielectric fluid added to the fluidic passages; and

a circulating mechanism configured to circulate the dielectric fluid through the transistor plane.

2. The microfabrication device of claim 1 , wherein the solid-state dielectric materials are silicon oxide or silicon nitride.

3. The microfabrication device of claim 2 , wherein the removing the at least a portion of solid-state dielectric materials includes etching the portion of solid-state dielectric materials through one or more access shafts.

4. The microfabrication device of claim 3 , wherein the formation of the fluidic passages further includes closing the one or more access shafts after removing the at least a portion of solid-state dielectric materials.

5. A microfabrication device comprising:

a package structure on an array of semiconductor devices on a substrate;

first set of fluidic passages formed between the package and the array of semiconductor devices on the substrate;

second set of fluidic passages formed between cavities within the array of semiconductor devices, wherein the second set of fluidic passages have been formed from removal of at least a portion of solid-state dielectric materials surrounding the array of semiconductor devices;

dielectric fluid added to the first set of fluidic passages and the second set of fluidic passages; and

a circulating mechanism configured to circulate the dielectric fluid through the first set of fluidic passages and the second set of fluidic passages to transfer heat.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2021
From: CHANEMOUGAME, DANIEL; LIEBMANN, LARS; SMITH, JEFFREY; GUTWIN, PAUL
To: TOKYO ELECTRON LIMITED
Reel/Frame 056502/0422 →
Continuity (2)
Provisional Application 63137443 · Jan 14, 2021
Related Publication 20220223496A1 · Jul 14, 2022