Backside conducting lines in integrated circuits

1. An integrated circuit comprising:

a first-type active-region structure and a second-type active-region structure extending in a first direction on a substrate;

a front-side first-layer conducting line in a first connection layer above the substrate;

a plurality of gate-conductors extending in a second direction below the first connection layer, and wherein two adjacent gate-conductors are separated by a pitch distance equal to a contacted poly pitch (“CPP”);

a circuit cell having a first vertical boundary and a second vertical boundary extending in the second direction perpendicular to the first direction, wherein each of the first vertical boundary and the second vertical boundary crosses at least one boundary isolation region, and wherein a distance between the first vertical boundary and the second vertical boundary along the first direction is less than or equal to three CPPs;

a backside horizontal conducting line extending in the first direction in a backside first conducting layer below the substrate, wherein the backside horizontal conducting line extends across the first vertical boundary of the circuit cell;

a backside vertical conducting line extending in the second direction in a backside second conducting layer below the backside first conducting layer, wherein the backside vertical conducting line is aligned with the first vertical boundary; and

a pin-connector for the circuit cell directly connected between the backside horizontal conducting line and the backside vertical conducting line.

2. The integrated circuit of claim 1 , wherein the backside horizontal conducting line extends across the first vertical boundary of the circuit cell by a distance that is less than one CPP but more than one eighth of the CPP.

3. The integrated circuit of claim 1 , wherein the backside horizontal conducting line extends across the first vertical boundary of the circuit cell by a distance that is less than one CPP but more than one fourth of the CPP.

4. The integrated circuit of claim 1 , wherein the backside horizontal conducting line extends across the first vertical boundary of the circuit cell by a distance that is less than one CPP but more than one half of the CPP.

5. The integrated circuit of claim 1 , wherein the backside vertical conducting line has a width along the first direction that is larger than three fourths of the CPP.

6. The integrated circuit of claim 1 , wherein the backside vertical conducting line has a width along the first direction that is larger than one half of the CPP.

7. The integrated circuit of claim 1 , wherein the distance between the first vertical boundary and the second vertical boundary along the first direction is less than or equal to two CPPs.

8. An integrated circuit comprising:

a first-type active-region structure and a second-type active-region structure extending in a first direction on a substrate;

a front-side first-layer conducting line in a first connection layer above the substrate;

a plurality of gate-conductors extending in a second direction below the first connection layer, and wherein two adjacent gate-conductors are separated by a pitch distance equal to a contacted poly pitch (“CPP”),

circuit cell having a first vertical boundary and a second vertical boundary extending in the second direction perpendicular to the first direction, wherein each of the first vertical boundary and the second vertical boundary crosses at least one boundary isolation region;

a backside horizontal conducting line extending in the first direction in a backside first conducting layer below the substrate;

a backside vertical conducting line extending in the second direction in a backside second conducting layer below the backside first conducting layer;

a pin-connector for the circuit cell directly connected between the backside horizontal conducting line and the backside vertical conducting line at an overlap region between the backside horizontal conducting line and the backside vertical conducting line; and

wherein the backside vertical conducting line has a first portion covering the overlap region and a second portion outside the overlap region, and wherein a first width of the first portion along the first direction is larger than a second width of the second portion along the first direction.

9. The integrated circuit of claim 8 , wherein the first width is larger than the second width by an amount that is more than one eighth of the CPP.

10. The integrated circuit of claim 8 , wherein the first width is larger than the second width by an amount that is more than one fourth of the CPP.

11. The integrated circuit of claim 8 , wherein the first vertical boundary and the second vertical boundary are separated by a distance along the first direction that is less than or equal to three CPPs.

12. The integrated circuit of claim 8 , wherein the first vertical boundary and the second vertical boundary are separated by a distance along the first direction that is less than or equal to two CPPs.

13. The integrated circuit of claim 8 , wherein the backside horizontal conducting line extends across the first vertical boundary of the circuit cell by a distance that is less than one CPP but more than one eighth of the CPP.

14. The integrated circuit of claim 8 , wherein the backside horizontal conducting line extends across the first vertical boundary of the circuit cell by a distance that is less than one CPP but more than one fourth of the CPP.

15. An integrated circuit comprising:

a first-type active-region structure and a second-type active-region structure extending in a first direction on a substrate;

a front-side first-layer conducting line in a first connection layer above the substrate;

a plurality of gate-conductors extending in a second direction below the first connection layer, and wherein two adjacent gate-conductors are separated by a pitch distance equal to a contacted poly pitch (“CPP”);

a circuit cell having a first vertical boundary and a second vertical boundary extending in the second direction perpendicular to the first direction, wherein each of the first vertical boundary and the second vertical boundary crosses at least one boundary isolation region, and wherein a distance between the first vertical boundary and the second vertical boundary along the first direction is less than or equal to two CPPs;

a backside horizontal conducting line extending in the first direction in a backside first conducting layer below the substrate, wherein the backside horizontal conducting line extends across the first vertical boundary of the circuit cell; and

a backside vertical conducting line extending in the second direction in a backside second conducting layer below the backside first conducting layer, wherein the backside vertical conducting line is aligned with the first vertical boundary, and wherein the backside vertical conducting line has a width along the first direction that is larger than one half of the CPP.

16. The integrated circuit of claim 15 , further comprising:

a pin-connector for the circuit cell directly connected between the backside horizontal conducting line and the backside vertical conducting line.

17. The integrated circuit of claim 15 , wherein the backside horizontal conducting line extends across the first vertical boundary of the circuit cell by a distance that is less than one CPP but more than one eighth of the CPP.

18. The integrated circuit of claim 15 , wherein the backside horizontal conducting line extends across the first vertical boundary of the circuit cell by a distance that is less than one CPP but more than one fourth of the CPP.

19. The integrated circuit of claim 15 , wherein the backside horizontal conducting line extends across the first vertical boundary of the circuit cell by a distance that is less than one CPP but more than one half of the CPP.

20. The integrated circuit of claim 15 , wherein the backside vertical conducting line has a width along the first direction that is larger than three fourths of the CPP.