IP Library › Granted Patent US 11,749,561
Granted Patent B2
US 11,749,561 · App. 17/344,528 · Granted Sep 5, 2023

Self-alignment etching of interconnect layers

Inventor: Suketu Arun Parikh (San Jose, CA)
Assignee: Applied Materials, Inc.
H01L21/7682H01L21/32139H01L21/76819H01L21/76837H01L21/76892
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Quick Facts
Patent No.
US 11,749,561
App. No.
17/344,528
Granted
Sep 5, 2023
Kind
B2
Abstract

A method for etching a metal containing feature is provided. Using a pattern mask, layers of material are etched to expose a portion of a metal containing feature. At least a portion of the exposed metal containing feature is etched, and is replaced by the growth of a filler dielectric. The etched portion of the metal containing feature and the filler dielectric reduce the unwanted conductivity between adjacent metal containing features.

Claims (32)

1. A method of etching a metal containing feature, comprising:

etching a portion of a plurality of interconnect layers through openings of a first patterned mask to form one or more structures, each adjacent structure is separated by a channel, wherein each of the one or more structures comprises a dielectric cap disposed above a stack metal;

depositing a dielectric liner around each of the one or more structures;

depositing a first filler dielectric over the dielectric liner and within the channel;

removing a portion of the first filler dielectric;

depositing an etch stop layer over the one or more structures;

depositing a second filler dielectric over the etch stop layer; and

selectively etching the dielectric cap to expose an underlying surface of the stack metal.

2. The method of claim 1 , wherein selectively etching the dielectric cap comprises etching a portion of the second filler dielectric and the dielectric cap through openings of a second patterned mask.

3. The method of claim 1 , further comprising depositing a metal containing feature over the exposed underlying surface of the stack metal.

4. The method of claim 3 , wherein the metal containing feature consists essentially of molybdenum (Mo), ruthenium (Ru), tungsten (W), cobalt (Co), nickel silicide (NiSi), copper (Cu), aluminum (Al), rhodium (Rh), iridium (Ir), or nickel (Ni).

5. The method of claim 3 , wherein depositing the metal containing feature over the exposed underlying surface of the stack metal comprises depositing a first metal containing feature over a first structure of the one or more structures, and depositing a second metal containing feature over a second structure of the one or more structures, wherein the second metal containing feature is wider than the first metal containing feature.

6. The method of claim 1 , wherein the first filler dielectric comprises a low k dielectric material.

7. The method of claim 1 , wherein removing the portion of the first filler dielectric comprises chemical mechanical polishing.

8. The method of claim 1 , wherein depositing the first filler dielectric over the dielectric liner and within the channel comprises forming air gaps within the channel.

9. The method of claim 1 , wherein:

the first filler dielectric comprises Si;

the dielectric cap comprises at least one of silicon oxide and silicon nitride;

the etch stop layer comprises silicon carbonitride; and

the dielectric liner comprises at least one of silicon carbonitride and a material containing one or more of silicon, oxygen, and nitrogen.

10. The method of claim 1 , wherein depositing the dielectric liner comprises depositing the dielectric liner having a thickness of about 10 to about 15 Å.

11. The method of claim 1 , wherein the plurality of interconnect layers comprises a metal liner disposed below the stack metal.

12. The method of claim 11 , wherein the metal liner comprises a metal selected from the group consisting of titanium, iridium, and platinum.

13. A method of etching a metal containing feature, comprising:

etching a portion of a plurality of interconnect layers through openings of a first patterned mask to form one or more structures, each adjacent structure is separated by a channel, wherein each of the one or more structures comprises a dielectric cap disposed above a stack metal;

depositing a dielectric liner around each of the one or more structures;

depositing a first filler dielectric over the dielectric liner and within the channel;

removing a portion of the first filler dielectric;

depositing a dielectric stop layer over the one or more structures;

forming openings in a second patterned mask, the openings of the second patterned mask are at least partially misaligned with the stack metal;

selectively etching the dielectric cap to expose an underlying surface of the stack metal; and

depositing a metal containing feature over the surface of the stack metal, wherein the metal containing feature is substantially aligned with the stack metal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2021
From: PARIKH, SUKETU ARUN
To: APPLIED MATERIALS, INC.
Reel/Frame 056504/0017 →
Continuity (3)
Continuation 16691453 · Nov 21, 2019
Provisional Application 62784263 · Dec 21, 2018
Related Publication 20210305087A1 · Sep 30, 2021