IP Library › Granted Patent US 12,536,420
Granted Patent B2
US 12,536,420 · App. 17/347,017 · Granted Jan 27, 2026

Low power generative adversarial network accelerator and mixed-signal time-domain MAC array

Inventors: Jie Gu (Evanston, IL); Zhengyu Chen (Evanston, IL)
Assignee: NORTHWESTERN UNIVERSITY
G06N3/063G06N3/045G06N3/088
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Quick Facts
Patent No.
US 12,536,420
App. No.
17/347,017
Granted
Jan 27, 2026
Kind
B2
Abstract

Systems and methods for a low-cost mixed-signal time-domain accelerator for generative adversarial network (GAN) are provided. In one aspect, a system includes a memory and a training management unit (TMU) in communication with the memory. The TMU is configured to manage a training sequence. The system includes a time-domain multiplication-accumulation (TDMAC) unit in communication with the TMU, wherein the TDMAC unit is configured to perform time-domain multiplier operations and time-domain accumulator operations.

Claims (14)

1 . An edge device, comprising:

a memory; and

a mixed-signal generative adversarial network (GAN) accelerator in communication with the memory,

wherein the GAN accelerator is configured to perform mixed-signal time-domain training,

wherein the GAN accelerator comprises an application-specific integrated circuit (ASIC) training management unit (TMU) in communication with the memory, wherein the ASIC TMU is configured to perform a training sequence comprising an adaptive training scheme, and comprises a time-domain multiplication-accumulation (TDMAC) unit in communication with the ASIC TMU,

wherein the TDMAC unit is configured to perform multiplication-accumulation operations of a convolutional neural network and a transpose convolutional neural network.

2 . The edge device of claim 1 , wherein the GAN accelerator is implemented on an 8-bit low-power application-specific integrated circuit (ASIC) chip.

3 . The edge device of claim 2 , wherein the 8-bit low-power ASIC chip comprises power consumption of less than 39 mW.

4 . The edge device of claim 1 , wherein the TDMAC unit comprises a 16-bit time-pulse based time-domain accumulator (TD-ACC) configured to perform the time-domain accumulator operation.

5 . The edge device of claim 4 , wherein the 16-bit time-pulse based TD-ACC comprises four 4-bit ring-based time accumulators.

6 . The edge device of claim 1 , wherein the TDMAC unit comprises an 8-bit time-domain multiplier (TD-MUL) configured to perform the time-domain multiplier operations wherein the TD-MUL comprises a subthreshold TD-MUL.

7 . The edge device of claim 6 , wherein the TD-MUL comprises four 4-bit multipliers.

8 . The edge device of claim 1 , wherein the ASIC TMU is configured as a finite state machine comprising 41 training stages.

9 . The edge device of claim 1 , wherein the ASIC TMU comprises modules for performing pooling operations, sigmoid operations, and data transpose operations.

Assignments (2)
CONFIRMATORY LICENSE Recorded Jan 30, 2025
From: NORTHWESTERN UNIVERSITY
To: NATIONAL SCIENCE FOUNDATION
Reel/Frame 070059/0328 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2021
From: GU, JIE; CHEN, ZHENGYU
To: NORTHWESTERN UNIVERSITY
Reel/Frame 056591/0561 →
Continuity (2)
Provisional Application 63039100 · Jun 15, 2020
Related Publication 20210390380A1 · Dec 16, 2021
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