Method for forming source/drain contacts
Semiconductor devices and methods of forming the same are provided. In one embodiments, a semiconductor device includes an n-type transistor region and a p-type transistor region. The n-type transistor region includes a first gate stack, a first gate spacer over sidewalls of the first gate stack, an n-type epitaxial feature in a source/drain (S/D) region of the n-type transistor region, and a first metal silicide layer over the n-type epitaxial feature. The p-type transistor region includes a second gate stack, a second gate spacer over sidewalls of the second gate stack, a p-type epitaxial feature in an S/D region of the p-type transistor region, a dopant-containing implant layer over the p-type epitaxial feature, and a second metal silicide layer over the dopant-containing implant layer. The dopant-containing implant layer includes a metallic dopant.
1. A semiconductor device, comprising:
an n-type transistor region including:
a first gate stack;
a first gate spacer over sidewalls of the first gate stack;
an n-type epitaxial feature in a source/drain (S/D) region of the n-type transistor region; and
a first metal silicide layer over the n-type epitaxial feature; and
a p-type transistor region including:
a second gate stack;
a second gate spacer over sidewalls of the second gate stack;
a p-type epitaxial feature in an S/D region of the p-type transistor region;
a dopant-containing implant layer over the p-type epitaxial feature, wherein the dopant-containing implant layer includes a metallic dopant; and
a second metal silicide layer over the dopant-containing implant layer,
wherein a top surface of the n-type epitaxial feature has a first concave profile, a top surface of the p-type epitaxial feature has a second concave profile, and a lowest point of the first concave profile is below a lowest point of the second concave profile.
2. The semiconductor device of claim 1 , wherein the metallic dopant is gallium (Ga).
3. The semiconductor device of claim 1 , wherein the p-type epitaxial feature and the dopant-containing implant layer both include silicon germanium (SiGe).
4. The semiconductor device of claim 1 , wherein the n-type epitaxial feature is substantially free of the metallic dopant.
5. The semiconductor device of claim 1 , wherein the dopant-containing implant layer further includes a non-metallic dopant.
6. The semiconductor device of claim 5 , wherein the non-metallic dopant is boron (B).
7. The semiconductor device of claim 1 , wherein the first and second metal silicide layers include different metallic elements.
8. The semiconductor device of claim 7 , wherein the second metal silicide layer includes the metallic dopant and the first metal silicide layer is substantially free of the metallic dopant.
9. The semiconductor device of claim 1 , wherein a first vertical distance between a bottom surface of the first gate spacer and the lowest point of the first concave profile is greater than a second vertical distance between a bottom surface of the second gate spacer and the lowest point of the second concave profile.
10. The semiconductor device of claim 1 , wherein the lowest point of the first concave profile is below the lowest point of the second concave profile for at least 5 nm.
11. A semiconductor device, comprising:
a fin protruding from a substrate, the fin having a first source/drain (S/D) region, a second S/D region, and a channel region connecting the first and second S/D regions;
a gate structure over the channel region of the fin;
a first S/D feature comprising silicon germanium (SiGe) disposed in the first S/D region of the fin, wherein a top portion of the first S/D feature is doped with gallium (Ga) and a bottom portion of the first S/D feature is free of Ga;
a second S/D feature disposed in the second S/D region of the fin, wherein the second S/D feature is free of Ga, and wherein in cross-sectional views each along a lengthwise direction of the gate structure, a top surface of the first S/D feature is below a top surface of the second S/D feature;
a metal silicide layer over the top surface of the first S/D feature; and
an S/D contact disposed on the metal silicide layer and electrically coupled to the first S/D feature.
12. The semiconductor device of claim 11 , wherein in a cross-sectional view along a lengthwise direction of the fin, a top surface of the first S/D feature has a concave profile with a lowest point below a top surface of the fin.
13. The semiconductor device of claim 11 , wherein the top portion of the first S/D feature is also doped with boron (B).
14. The semiconductor device of claim 11 , further comprising:
a gate spacer layer disposed on sidewalls of the gate structure;
a contact etch stop layer (CESL) disposed on sidewalls of the gate spacer layer; and
a protective dielectric layer interposing the CESL and the S/D contact.
15. The semiconductor device of claim 11 , wherein in a cross-sectional view along a lengthwise direction of the fin, the top surface of the first S/D feature has a concave profile, and the top surface of the second S/D feature is substantially flat.
16. The semiconductor device of claim 11 , wherein in the cross-sectional views each along the lengthwise direction of the gate structure, the top surface of the first S/D feature and the top surface of the second S/D feature each have a rhombus profile.
17. The semiconductor device of claim 11 , wherein the second S/D feature includes SiGe.
18. A semiconductor device comprising:
an n-type FinFET region including:
a first gate stack;
a first gate spacer over sidewalls of the first gate stack;
an n-type epitaxial feature in a source/drain (S/D) region of the n-type FinFET region; and
a first metal silicide layer over the n-type epitaxial feature; and
a p-type FinFET region including:
a second gate stack;
a second gate spacer over sidewalls of the second gate stack;
a silicon germanium (SiGe) epitaxial feature in an S/D region of the p-type FinFET region, wherein a top portion of the SiGe epitaxial feature includes gallium (Ga); and
a second metal silicide layer over the top portion of the SiGe epitaxial feature,
wherein a top surface of the n-type epitaxial feature has a first concave profile, a top surface of the SiGe epitaxial feature has a second concave profile, and a lowest point of the first concave profile is below a lowest point of the second concave profile.
19. The semiconductor device of claim 18 , wherein the SiGe epitaxial feature further includes boron (B).
20. The semiconductor device of claim 18 , wherein a first vertical distance between a bottom surface of the first gate spacer and the lowest point of the first concave profile is greater than a second vertical distance between a bottom surface of the second gate spacer and the lowest point of the second concave profile.