Amorphous silicon-based scavenging and sealing EOT
A sacrificial sealing layer is formed on a high-κ metal gate (HKMG) stack to suppress oxidants, e.g., oxygen and water, from impacting the metal gate stack, thus preserving the device EOT. The method integrated processes that include forming an interfacial layer on the substrate; forming a high-κ metal oxide layer on the interfacial layer, the high-κ metal oxide layer comprising a dipole region adjacent to the interfacial layer, the dipole region; depositing a capping layer on the high-κ metal oxide layer; and forming a sacrificial sealing layer on the capping layer. The dipole region is formed by driving a dopant species, e.g., zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium (Ti), tantalum (Ta), zirconium (Zr), aluminum (Al), niobium (Nb), or mixtures thereof, of a dipole film into the high-κ metal oxide layer to form a dipole region.
1. A method of forming a metal gate stack, the method comprising:
forming an interfacial layer on a surface of a substrate;
depositing a high-κ metal oxide layer on the interfacial layer;
forming a dipole film on the high-k metal oxide layer;
depositing a first capping layer on the substrate;
forming a sacrificial sealing layer on the first capping layer;
exposing the substrate to a thermal treatment at a temperature of at least 700° C. to drive the dipole film into the high-κ metal oxide layer and to form a dipole region on the metal gate stack, wherein the metal gate stack has an equivalent oxide thickness (EOT) increase that is less than or equal to 0.2 Å relative to a metal gate stack having no sacrificial sealing layer thereon; and
removing the sacrificial sealing layer.
2. The method of claim 1 , wherein the sacrificial sealing layer comprises amorphous silicon (a-Si).
3. The method of claim 1 , wherein the sacrificial sealing layer has a thickness in a range of from 5 Å to 50 Å.
4. The method of claim 1 , wherein the dipole film comprises a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal.
5. The method of claim 4 , wherein the dipole metal comprises zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium (Ti), tantalum (Ta), zirconium (Zr), aluminum (Al), niobium (Nb), or mixtures thereof.
6. The method of claim 1 , further comprising removing any remaining portion of the dipole film, and the first capping layer.
7. The method of claim 6 , further comprising depositing a second capping layer on the substrate.
8. The method of claim 7 , further comprising depositing a PMOS work function material on the substrate.
9. The method of claim 8 , further comprising depositing a gate material on the substrate.
10. The method of claim 1 , wherein the first capping layer comprises titanium nitride (TiN) or titanium silicon nitride (TiSiN).
11. The method of claim 1 , wherein the high-k metal oxide layer comprises one or more of hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), hafnium zirconium oxide (HfZrO), hafnium zirconium oxynitride (HfZrON), hafnium silicon oxide (HfSiO), and hafnium silicon oxynitride (HfSiON).
12. The method of claim 1 , wherein the interfacial layer comprises one or more of silicon dioxide (SiO 2 ), silicon germanium oxide (SiGeO x ), germanium oxide (GeO x ), or silicon oxynitride (SiON).
13. A method of scavenging oxidants from a metal gate stack, the method comprising:
forming a sacrificial sealing layer on the metal gate stack, the metal gate stack comprising a first capping layer on a dipole film on high-k metal oxide layer on an interfacial layer on a surface of a substrate;
exposing the metal gate stack to a thermal treatment at a temperature of at least 700° C. to drive the dipole film into the high-κ metal oxide layer and to form a dipole region, wherein the metal gate stack has an equivalent oxide thickness (EOT) increase that is less than or equal to 0.2 Å relative to a metal gate stack having no sacrificial sealing layer thereon; and
removing the sacrificial sealing layer.
14. The method of claim 13 , wherein the sacrificial sealing layer comprises amorphous silicon (a-Si).
15. The method of claim 13 , wherein the sacrificial sealing layer has a thickness in a range of from 5 Å to 50 Å.
16. The method of claim 13 , further comprising removing any remaining portion of the dipole film, and the first capping layer.
17. The method of claim 13 , further comprising depositing a second capping layer on the substrate.
18. The method of claim 17 , further comprising depositing a PMOS work function material on the substrate.
19. The method of claim 18 , further comprising depositing a gate material on the substrate.