Extended error detection for a memory device
Methods, systems, and devices for extended error detection for a memory device are described. For example, during a read operation, the memory device may perform an error detection operation capable of detecting single-bit errors, double-bit errors, and errors that impact more than two bits and indicate the detected error to a host device. The memory device may use parity information to perform an error detection procedure to detect and/or correct errors within data retrieved during the read operation. In some cases, the memory device may associate each bit of the data read during the read operation with two or more bits of parity information. For example, the memory device may use two or more sets of parity bits to detect errors within a matrix of the data. Each set of parity bits may correspond to a dimension of the matrix of data.
1. A method, comprising:
receiving, at a memory device via an interface, a write command comprising data to be written to one or more memory cells of the memory device;
generating, based at least in part on receiving the write command, error information comprising a first set of parity bits corresponding to a first subset of the data and a second set of parity bits corresponding to a second subset of the data;
storing, to the one or more memory cells of the memory device, the first set of parity bits and the second set of parity bits based at least in part on generating the error information;
receiving, at the memory device, a read command for the data based at least in part on generating the error information; and
performing an error detection operation based at least in part on receiving the read command, wherein the error detection operation comprises comparing two or more of the first set of parity bits, the second set of parity bits, or a third set of parity bits.
2. The method of claim 1 , wherein the first set of parity bits, the second set of parity bits, and the data are stored to a same sub-array or a same row of the memory device.
3. The method of claim 1 , further comprising:
reading the data from the one or more memory cells of the memory device based at least in part on receiving the read command; and
reading the first set of parity bits and the second set of parity bits from the one or more memory cells of the memory device based at least in part on reading the data, wherein performing the error detection operation is based at least in part on reading the data from the one or more memory cells of the memory device and reading the first set of parity bits and the second set of parity bits from the one or more memory cells of the memory device.
4. The method of claim 3 , wherein performing the error detection operation comprises:
generating the third set of parity bits based at least in part on reading the data from the one or more memory cells of the memory device; and
comparing two or more of the first set of parity bits, the second set of parity bits, and the third set of parity bits based at least in part on generating the third set of parity bits.
5. The method of claim 1 , further comprising:
transmitting second data, wherein at least a portion of the second data is transmitted concurrent with performing the error detection operation; and
transmitting an indication of an error associated with the data from the one or more memory cells of the memory device based at least in part on performing the error detection operation.
6. The method of claim 5 , further comprising:
detecting the error associated with the data from the one or more memory cells from the memory device while at least a portion of the second data is being transmitted, wherein the indication of the error associated with the data is transmitted after the second data is transmitted.
7. A method, comprising:
receiving, at a memory device via an interface, a write command comprising data to be written to one or more memory cells of the memory device;
generating, based at least in part on receiving the write command, error information comprising a first set of parity bits corresponding to a first subset of the data and a second set of parity bits corresponding to a second subset of the data;
receiving, at the memory device, a read command for the data based at least in part on generating the error information;
performing an error detection operation based at least in part on receiving the read command, wherein the error detection operation comprises comparing two or more of the first set of parity bits, the second set of parity bits, or a third set of parity bits;
correcting at least one error associated with the data based at least in part on performing the error detection operation, wherein the at least one error comprises a single-bit error, a double-bit error, or an error associated with more than two bits; and
transmitting the corrected data based at least in part on correcting the at least one error associated with the data.
8. A method, comprising:
generating, at a memory device, a first set of parity bits based at least in part on receiving a write command comprising data to be written to a sub-array of the memory device;
storing the first set of parity bits to the sub-array of the memory device based at least in part on generating the first set of parity bits;
receiving a read command for the data stored to the sub-array of the memory device;
generating a second set of parity bits based at least in part on receiving the read command for the data stored to the sub-array of the memory device; and
performing an error detection operation based at least in part on receiving the read command, wherein the error detection operation comprises comparing the first set of parity bits with the second set of parity bits based at least in part on generating the second set of parity bits, wherein the data stored to the sub-array of the memory device comprises an error based at least in part on one bit of the first set of parity bits being different than a corresponding bit of the second set of parity bits.
9. The method of claim 8 , further comprising:
reading the first set of parity bits from the sub-array of the memory device; and
determining that each parity bit of the first set of parity bits matches each corresponding bit of the second set of parity bits.
10. A method, comprising:
generating, at a memory device, a first set of parity bits based at least in part on receiving a write command comprising data to be written to a sub-array of the memory device;
storing the first set of parity bits to the sub-array of the memory device based at least in part on generating the first set of parity bits;
receiving a read command for the data stored to the sub-array of the memory device;
reading the first set of parity bits from the sub-array of the memory device;
generating a second set of parity bits based at least in part on receiving the read command for the data stored to the sub-array of the memory device; and
performing an error detection operation based at least in part on receiving the read command, wherein the error detection operation comprises determining that at least one bit of the first set of parity bits is different than a corresponding bit of the second set of parity bits.
11. The method of claim 10 , further comprising:
correcting an error associated with the data stored to the sub-array of the memory device based at least in part on determining that at least one bit of the first set of parity bits is different than a corresponding bit of the second set of parity bits; and
transmitting the corrected data based at least in part on correcting the error.
12. An apparatus, comprising:
a memory array comprising a plurality of memory cells; and
a controller coupled with an array of memory cells and configured to:
receive a command;
read data, a first set of parity bits, and a second set of parity bits from the memory array based at least in part on receiving the command, each parity bit of the first set of parity bits corresponding to parity information for a respective first subset of the data and each parity bit of the second set of parity bits corresponding to parity information for a respective second subset of the data, wherein the respective first subsets are associated with a first dimension of a matrix of the data and the respective second subsets are associated with a second dimension of the matrix of the data;
perform an error detection operation on the data read from the memory array based at least in part on the first set of parity bits and the second set of parity bits; and
output an indicator of an error based at least in part on performing the error detection operation.
13. The apparatus of claim 12 , wherein the controller is configured to:
read a third set of parity bits from the memory array based at least in part on receiving the command, wherein the second set of parity bits corresponds to parity information for the second dimension for a first portion of the data and the third set of parity bits corresponds to parity information for the second dimension for a second portion of the data that is different than the first portion of the data.
14. The apparatus of claim 12 , wherein the controller is configured to:
read a third set of parity bits from the memory array based at least in part on the command, the third set of parity bits corresponding to parity information for a third dimension of the matrix of the data,
wherein the performing the error detection operation is based at least in part on the third set of parity bits.
15. An apparatus comprising:
a memory array comprising a plurality of memory cells; and
a controller coupled with an array of memory cells and configured to:
receive a command;
read data, a first set of parity bits, and a second set of parity bits from the memory array based at least in part on receiving the command, each parity bit of the first set of parity bits corresponding to parity information for a respective first subset of the data and each parity bit of the second set of parity bits corresponding to parity information for a respective second subset of the data;
perform an error detection operation on the data read from the memory array based at least in part on the first set of parity bits and the second set of parity bits;
obtain second data based at least in part on the data read from the memory array and the first set of parity bits and the second set of parity bits; and
output the second data and an indicator of an error based at least in part on performing the error detection operation.
16. The apparatus of claim 12 , wherein the controller is configured to:
determine that the memory array is operating in a first mode, wherein the first mode is associated with a lower latency than a second mode; and
output the data read from the memory array based at least in part on the determining, wherein the outputting comprises bypassing an error correction operation.
17. The apparatus of claim 12 , wherein the controller is configured to:
perform at least one of a single error correction (SEC) operation or a single error correction double error detection (SECDED) operation on the data read from the memory array to obtain second data; and
output the second data.