Bit efficient memory error correcting coding and decoding scheme
Aspects of the disclosed technology include techniques and mechanisms for an efficient error correction coding scheme that can detect and correct data errors that may occur in a memory. In general, the scheme comprises segmenting the data that would be transferred as part of a data request into different parts and applying error correction codes to the separate parts.
1. A method for encoding data associated with a request access for one or more DRAMs, comprising:
segmenting a number of beats defined for a burst access to the one or more DRAMs into at least a first set of beats and a second set of beats;
defining a first set of error correction code (ECC) for a first set of data associated with the first set of beats; and
defining a second set of ECC for a second set of data associated with the second set of beats;
wherein one of the first set of ECC comprises a first set of symbols, each symbol of the first set being associated with the first set of beats,
wherein one of the second set of ECC comprises a second set of symbols, each symbol of the second set of symbols being associated with the second set of beats, wherein the first set of symbols comprises a different number of symbols than the second set of symbols and an error associated with the second set of ECC is correctable using information of the first set of ECC, and wherein the second set of ECC comprises one or more symbols used for storing metadata, the metadata being associated with a memory tag extension.
2. The method of claim 1 , wherein the first set of beats and the second set of beats equal the number of beats defined for the burst access.
3. The method of claim 1 , wherein the one or more DRAMs comprise DDR5 DRAMs and the number of beats defined for the burst access comprises 16 beats.
4. The method of claim 3 , wherein the first set of beats and second set of beats each comprise 8 beats.
5. The method of claim 4 , wherein the one or more DRAMs each include 4 data pins.
6. The method of claim 5 , wherein the one or more DRAMs comprise 10 DRAMs and the first set of error correction code comprises a Reed Solomon with code 8 ECCs for 32 data symbols and 8 bits/symbol such as RS (40, 32, 8).
7. The method of claim 6 , wherein the second set of error correction code comprises a Reed Solomon code with 8 ECCs for 32 data symbols and 8 bits/symbol such as RS(40, 32, 8).
8. The method of claim 7 , comprising defining a second 4 byte symbol associated with the second set of ECC, the second 4 byte symbol comprising the metadata.
9. The method of claim 1 , wherein the number of the second set of symbols is half the number of the first set of symbols.
10. A memory system, comprising:
one or more DRAMs; and
a memory controller communicatively coupled to the one or more DRAMs, the memory controller having logic that implements the following function in response to a request access to the one or more DRAMs:
segment a number of beats defined for a burst access to the one or more DRAMs in at least a first set of beats and a second set of beats;
define a first set of error correction code (ECC) for a first set of data associated with the first set of beats;
define a second set of ECC for a second set of data associated with the second set of beats;
wherein one of the first set of ECC comprises a first set of symbols, each symbol of the first set being associated with the first set of beats,
wherein one of the second set of ECC comprises a second set of symbols, each symbol of the second set of symbols being associated with the second set of beats, wherein the first set of symbols comprises a different number of symbols than the second set of symbols and an error associated with the second set of ECC is correctable using information of the first set of ECC, and wherein the second set of ECC comprises one or more symbols used for storing metadata, the metadata being associated with a memory tag extension.
11. The memory system of claim 10 , wherein the first set of beats and the second set of beats equal the number of beats defined for the burst access.
12. The memory system of claim 10 , wherein the one or more DRAMs comprises DDR5 DRAMs and the number of beats defined for the burst access comprises 16 beats.
13. The memory system of claim 12 , wherein the first set of beats and the second set of beats each comprise 8 beats.
14. The memory system of claim 13 , wherein the one or more DRAMs each include 4 data pins.
15. The memory system of claim 14 , wherein the one or more DRAMs comprise 10 DRAMs and the first set of error correction code comprises a Reed Solomon code with 8 ECCs for 32 data symbols and 8 bits/symbol such as RS (40, 32, 8).
16. The memory system of claim 14 , wherein the second set of error correction code comprises a Reed Solomon code with 8 ECCs for 32 data symbols and 8 bits/symbol such as RS (40, 32, 8).
17. The memory system of claim 16 , wherein the logic functions to define a second 4 byte symbol associated with the second set of ECC, the second 4 byte symbol comprising the metadata.
18. The memory system of claim 10 , wherein the logic comprises hardware logic comprising an encoder and a decoder.
19. The memory system of claim 18 , wherein the encoder encodes the first set of data using the first set of ECC in a first cycle of a 64 byte transaction and the encoder encodes the second set of data using the second set of ECC in a second cycle of the 64 byte transaction.
20. The memory system of claim 18 , wherein the decoder decodes the first set of data using the first set of ECC in a first cycle of a 64 byte transaction and the decoder decodes the second set of data using the second set of ECC in a second cycle of the 64 byte transaction.