Lateral high voltage SCR with integrated negative strike diode
An SCR with a first semiconductor region and plural concentric semiconductor regions, each surrounding the first semiconductor region. The SCR also includes, surrounded by at least one concentric semiconductor region in the plurality of concentric semiconductor regions, an electrically non-contacted region of a semiconductor type and positioned to modulate a snapback voltage of the silicon controlled rectifier and an electrically-contacted region of the semiconductor type and positioned to provide a diodic response between the at least one concentric semiconductor region in the plurality of concentric semiconductor regions and the electrically-contacted region.
1. A silicon controlled rectifier (SCR), comprising:
a first semiconductor region;
a second semiconductor region circumscribing the first semiconductor region;
an electrically non-contacted region of a semiconductor type and partially surrounding the second semiconductor region, the electrically non-contacted region configured to provide a snapback operation of the silicon controlled rectifier; and
an electrically-contacted region of the semiconductor type and located adjacent to a side of the second semiconductor region and configured to provide a diodic operation of the silicon controlled rectifier, wherein a plurality of concentric semiconductor regions surrounds the electrically non-contacted region and the electrically-contacted region.
2. The SCR of claim 1 , further comprising, an SCR anode coupled to the first semiconductor region and to the electrically-contacted region.
3. The SCR of claim 1 , wherein:
the second semiconductor region provides an emitter for a PNP bipolar junction transistor (BJT);
a first concentric semiconductor region of the plurality of concentric semiconductor regions provides a collector for the PNP BJT; and
the electrically non-contacted region is positioned between the first concentric semiconductor region and the second semiconductor region.
4. The SCR of claim 1 , wherein:
the first semiconductor region provides a collector for an NPN bipolar junction transistor (BJT);
a second concentric semiconductor region of the plurality of concentric semiconductor regions provides an emitter for the NPN BJT; and
the electrically non-contacted region is positioned between the first semiconductor region and the second concentric semiconductor region.
5. The SCR of claim 1 , wherein:
the first semiconductor region provides a collector for an NPN bipolar junction transistor (BJT);
the second semiconductor region provides an emitter for a PNP BJT;
a first concentric semiconductor region of the plurality of concentric semiconductor regions provides a collector for the PNP BJT;
a second concentric semiconductor region of the plurality of concentric semiconductor regions provides an emitter for the NPN BJT, the second concentric semiconductor region located in the first concentric semiconductor region; and
the electrically non-contacted region is positioned between the second semiconductor region and the first concentric semiconductor region.
6. The SCR of claim 5 , wherein the electrically non-contacted region is positioned between the second semiconductor region and the second concentric semiconductor region.
7. The SCR of claim 1 , wherein:
the electrically non-contacted region of the semiconductor type is positioned at a first closest distance from a first concentric semiconductor region of the plurality of concentric semiconductor regions; and
the electrically-contacted region of the semiconductor type is positioned at a second distance greater than the first distance from the first concentric semiconductor region of the plurality of concentric semiconductor regions.
8. The SCR of claim 7 , wherein the second distance is greater than the first distance by a factor of two to three.
9. The SCR of claim 7 , wherein:
the electrically non-contacted region of the semiconductor type is positioned at a third distance from a second concentric semiconductor region of the plurality of concentric semiconductor regions, the third distance greater than the first distance; and
the electrically-contacted region of the semiconductor type is positioned at a fourth distance greater than the second distance from the second concentric semiconductor region of the plurality of concentric semiconductor regions, the fourth distance greater than the third distance.
10. The SCR of claim 1 , wherein:
a second concentric semiconductor region of the plurality of concentric semiconductor regions provides an emitter for an NPN bipolar junction transistor (BJT); and
a first concentric semiconductor region of the plurality of concentric semiconductor regions provides a collector for a PNP BJT.
11. The SCR of claim 1 , wherein the electrically non-contacted region presents a U-shaped configuration from a plan perspective.
12. The SCR of claim 1 , wherein the electrically-contacted region presents a linear configuration from a plan perspective.
13. The SCR of claim 1 , wherein:
the electrically non-contacted region presents a U-shaped configuration from a plan perspective; and
the electrically-contacted region presents a linear configuration from the plan perspective.
14. The SCR of claim 1 , further comprising:
a trench isolation region surrounding the plurality of concentric semiconductor regions.
15. The SCR of claim 1 , wherein:
a second concentric semiconductor region of the plurality of concentric semiconductor regions provides an emitter for an NPN bipolar junction transistor (BJT);
a first concentric semiconductor region of the plurality of concentric semiconductor regions provides a collector for a PNP BJT; and
the SCR includes a p type well in which the first concentric semiconductor region and the second concentric semiconductor region are formed.
16. The SCR of claim 15 , further comprising:
an n type epi layer in which the p type well is formed.
17. The SCR of claim 1 , wherein the plurality of concentric semiconductor regions includes a concentric isolation region.
18. The SCR of claim 1 , wherein the snapback operation includes a breakdown of a junction between a first concentric semiconductor region of the plurality of concentric semiconductor regions and an epi layer in which the first concentric semiconductor region is located.
19. The SCR of claim 1 , wherein the snapback operation includes a current path through the electrically non-contacted region.
20. the SCR of claim 1 , wherein the diodic operation includes forward-biasing a diode formed between a first concentric semiconductor region of the plurality of concentric semiconductor regions and the electrically-contacted region.
21. The SCR of claim 1 , wherein the diodic operation includes a current path through the electrically-contacted region.
22. The SCR of claim 1 , wherein:
the snapback operation is in response to a first electrostatic discharge pulse at the first semiconductor region, the first electrostatic discharge pulse having a first polarity; and
the diodic operation is in response to a second electrostatic discharge pulse at the first semiconductor region, the second electrostatic discharge pulse having a second polarity opposite the first polarity.