IP Library Granted Patent US 12,362,570
Granted Patent B2
US 12,362,570 · App. 17/348,692 · Granted Jul 15, 2025

Multiple port DC-DC converter

Inventors: Al-Thaddeus Avestruz (Ann Arbor, MI); Alireza Ramyar (Ann Arbor, MI)
Assignee: The Regents of the University of Michigan
H02J3/381H02M1/08H02M3/33569H02J2300/26
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Quick Facts
Patent No.
US 12,362,570
App. No.
17/348,692
Granted
Jul 15, 2025
Kind
B2
Abstract

A device for DC-DC conversion includes a plurality of input ports to receive a set of DC voltage inputs, at least one DC voltage input being configured as a differential input, a plurality of input semiconductor switches, each input semiconductor switch being coupled to a respective input port of the plurality of input ports, an inductor coupled to each input semiconductor switch, a pair of output semiconductor switches coupled to the inductor, an output coupled to the inductor via the pair of output semiconductor switches, and a processor configured to generate input switch control signals for the plurality of input semiconductor switches to sequentially and selectively connect each DC voltage input to the inductor to charge the inductor and to generate an output switch control signal for the pair of output semiconductor switches to connect the inductor to the output to discharge the inductor via the output.

Claims (40)

1. A device for DC-DC conversion, the device comprising:

a plurality of input ports configured to receive a set of DC voltage inputs, the plurality of input ports comprising at least one differential input port;

a plurality of input semiconductor switches, each input semiconductor switch of the plurality of input semiconductor switches being coupled to a respective input port of the plurality of input ports;

an inductor coupled to each input semiconductor switch of the plurality of input semiconductor switches;

a pair of output semiconductor switches coupled to the inductor;

an output coupled to the inductor via the pair of output semiconductor switches; and

a processor configured to generate input switch control signals for the plurality of input semiconductor switches to sequentially and selectively connect each DC voltage input of the set of DC voltage inputs to the inductor to charge the inductor and to generate an output switch control signal for the pair of output semiconductor switches to connect the inductor to the output to discharge the inductor via the output.

2. The device of claim 1 , wherein the input switch control signals and the output switch control signal establish an input duty cycle for each DC voltage input of the set of DC voltage inputs and an output duty cycle for the output.

3. The device of claim 1 , wherein the output is not isolated from the plurality of input ports by a transformer.

4. The device of claim 1 , wherein the processor is configured to generate the input switch control signals without a current measurement from a current sensor.

5. The device of claim 1 , wherein the processor is configured to adjust the input switch control signals and the output switch control signal in accordance with an optimization procedure.

6. The device of claim 5 , wherein the optimization procedure is configured as a gradient search procedure for maximum power point tracking.

7. The device of claim 5 , wherein the optimization procedure is configured as a coordinate ascent procedure for maximum power point tracking.

8. The device of claim 5 , wherein the optimization procedure is based on a measurement of an output voltage at the output and a measurement of a respective DC voltage input of the set of DC voltage inputs.

9. The device of claim 5 , wherein the optimization procedure implements a control scheme having a reference voltage for the respective DC voltage input and a linear combination of duty cycles for the set of DC voltage inputs as control variables.

10. The device of claim 5 , wherein the optimization procedure generates an input duty cycle for each DC voltage input of the set of DC voltage inputs and an output duty cycle for the output.

11. The device of claim 1 , further comprising a capacitor coupled to the output such that discharging the inductor charges the capacitor.

12. The device of claim 1 , wherein all but one of the plurality of input ports are configured as differential input ports.

13. A system for power processing, the system comprising:

a plurality of power sources, each power source of the plurality of power sources providing a power source voltage; and

a DC-DC converter coupled to the plurality of power sources, wherein the DC-DC converter comprises:

a plurality of input ports to receive the power supply voltages from the plurality of power supplies;

a plurality of input semiconductor switches, each input semiconductor switch of the plurality of input semiconductor switches being coupled to a respective input port of the plurality of input ports;

an inductor coupled to each input semiconductor switch of the plurality of input semiconductor switches;

a pair of output semiconductor switches coupled to the inductor;

an output coupled to the inductor via the pair of output semiconductor switches; and

a processor configured to generate input switch control signals for the plurality of input semiconductor switches to sequentially and selectively connect a respective pair of input ports of the plurality of input ports to the inductor to charge the inductor and to generate an output switch control signal for the pair of output semiconductor switches to connect the inductor to the output port to discharge the inductor to a load coupled to the output;

wherein at least one of the power source voltages provided by the plurality of power sources is a differential voltage.

14. The system of claim 13 , wherein the input switch control signals and the output switch control signal establish an input duty cycle for current provided by each pair of input ports of the plurality of input ports and an output duty cycle for the output.

15. The system of claim 13 , wherein each power source of the plurality of power sources comprises a solar photovoltaic cell.

16. The system of claim 13 , wherein each power source of the plurality of power sources comprises a plurality of solar photovoltaic cells.

17. The system of claim 13 , wherein the plurality of power sources are arranged in a differential diffusion charge redistribution architecture.

18. The system of claim 13 , wherein the plurality of power sources are arranged in a switched ladder architecture.

19. The system of claim 13 , the processor is configured to adjust the input switch control signals and the output switch control signal in accordance with an optimization procedure configured for maximum power point tracking of the plurality of power supplies.

20. A device for emulation of a plurality of solar photovoltaic cells, the device comprising:

a plurality of semiconductor device circuits, each semiconductor device circuit of the plurality of semiconductor device circuits being configured to replicate a diode string of a respective solar photovoltaic string of the plurality of solar photovoltaic cells; and

a plurality of current sources, each current source driving a respective semiconductor device circuit of the plurality of semiconductor device circuits;

wherein the plurality of current sources are configured for operation such that a sum of output currents from the plurality of semiconductor device circuits is constant and such that an output voltage for each semiconductor device circuit of the plurality of semiconductor device circuits is equal.

21. The device of claim 20 , wherein each semiconductor device circuit comprises a V be multiplier device.

22. The device of claim 21 , wherein each V be multiplier device comprises a Darlington bipolar junction transistor pair.

Assignments (2)
CONFIRMATORY LICENSE Recorded Nov 15, 2021
From: UNIVERSITY OF MICHIGAN
To: UNITED STATES DEPARTMENT OF ENERGY
Reel/Frame 058825/0752 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2021
From: AVESTRUZ, AL-THADDEUS; RAMYAR, ALIREZA
To: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
Reel/Frame 057574/0271 →
Continuity (2)
Provisional Application 63038992 · Jun 15, 2020
Related Publication 20210391726A1 · Dec 16, 2021
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