Semiconductor device and method of forming hybrid TIM layers
A semiconductor device has an electrical component and a first TIM with a first compliant property is disposed over a surface of the electrical component. A second TIM having a second compliant property greater than the first compliant property is disposed over the surface of the electrical component within the first TIM. A third TIM can be disposed over the surface of the electrical component along the first TIM. A heat sink is disposed over the first TIM and second TIM. The second TIM has a shape of a star pattern, grid of dots, parallel lines, serpentine, or concentric geometric shapes. The first TIM provides adhesion for joint reliability and the second TIM provides stress relief. Alternatively, a heat spreader is disposed over the first TIM and second TIM and a heat sink is disposed over a third TIM and fourth TIM on the heat spreader.
1. A method of making a semiconductor device, comprising:
providing an electrical component;
disposing a first thermal interface material (TIM) including a first compliant property over a surface of the electrical component around a perimeter of the electrical component; and
disposing a second TIM including a second compliant property greater than the first compliant property over the surface of the electrical component within the first TIM, wherein the second TIM is disposed relative to the first TIM to have a gap separating the first TIM and second TIM.
2. The method of claim 1 , further including:
providing an interconnect substrate; and
disposing the electrical component over the interconnect substrate.
3. The method of claim 1 , further including disposing a heat sink over the first TIM and second TIM.
4. A method of making a semiconductor device, comprising:
providing an electrical component;
disposing a first thermal interface material (TIM) including a first compliant property over a surface of the electrical component around a perimeter of the electrical component;
disposing a second TIM including a second compliant property greater than the first compliant property over the surface of the electrical component within the first TIM; and
disposing a third TIM over the surface of the electrical component along the first TIM.
5. The method of claim 1 , wherein the second TIM has a shape selected from the group consisting of a star pattern, grid of dots, parallel strips, serpentine, and concentric geometric shapes.
6. The method of claim 1 , wherein the first TIM provides adhesion for joint reliability and the second TIM provides stress relief.
7. A method of making a semiconductor device, comprising:
providing an electrical component;
disposing a first thermal interface material (TIM) having a first compliant property over a surface of the electrical component; and
disposing a second TIM having a second compliant property over the surface of the electrical component within the first TIM, wherein the second compliant property is greater than the first compliant property and the second TIM is disposed relative to the first TIM to have a space separating the first TIM and second TIM.
8. The method of claim 7 , further including:
providing an interconnect substrate; and
disposing the electrical component over the interconnect substrate.
9. The method of claim 7 , further including disposing a heat sink over the first TIM and second TIM.
10. The method of claim 7 , further including disposing a third TIM over the surface of the electrical component along the first TIM.
11. The method of claim 7 , wherein the second TIM has a shape selected from the group consisting of a star pattern, grid of dots, parallel strips, serpentine, and concentric geometric shapes.
12. The method of claim 7 , wherein the first TIM provides adhesion for joint reliability and the second TIM provides stress relief.
13. The method of claim 7 , further including:
disposing a heat spreader over the first TIM and second TIM;
disposing a third TIM having the first compliant property over a surface of the heat spreader;
disposing a fourth TIM having the second compliant property over the surface of the heat spreader within the first TIM; and
disposing a heat sink over the third TIM and fourth TIM.
14. A semiconductor device, comprising:
an electrical component;
a first thermal interface material (TIM) including a first compliant property disposed over a surface of the electrical component; and
a second TIM including a second compliant property greater than the first compliant property disposed over the surface of the electrical component within the first TIM, wherein the second TIM is disposed relative to the first TIM to have a gap separating the first TIM and second TIM.
15. The semiconductor device of claim 14 , further including an interconnect substrate, where the electrical component is disposed over the interconnect substrate.
16. The semiconductor device of claim 14 , further including a heat sink disposed over the first TIM and second TIM.
17. The semiconductor device of claim 14 , further including a third TIM disposed over the surface of the electrical component along the first TIM.
18. The semiconductor device of claim 14 , wherein the second TIM has a shape selected from the group consisting of a star pattern, grid of dots, parallel strips, serpentine, and concentric geometric shapes.
19. The semiconductor device of claim 14 , wherein the first TIM provides adhesion for joint reliability and the second TIM provides stress relief.
20. A semiconductor device, comprising:
an electrical component;
a first thermal interface material (TIM) having a first compliant property disposed over a surface of the electrical component; and
a second TIM having a second compliant property disposed over the surface of the electrical component within the first TIM, wherein the second compliant property is greater than the first compliant property and the second TIM is disposed relative to the first TIM to have a space separating the first TIM and second TIM.
21. The semiconductor device of claim 20 , further including a heat sink disposed over the first TIM and second TIM.
22. The semiconductor device of claim 20 , further including a third TIM disposed over the surface of the electrical component along the first TIM.
23. The semiconductor device of claim 20 , wherein the second TIM has a shape selected from the group consisting of a star pattern, grid of dots, parallel strips, serpentine, and concentric geometric shapes.
24. The semiconductor device of claim 20 , wherein the first TIM provides adhesion for joint reliability and the second TIM provides stress relief.
25. The semiconductor device of claim 20 , further including:
a heat spreader over the first TIM and second TIM;
a third TIM having the first compliant property disposed over a surface of the heat spreader;
a fourth TIM having the second compliant property disposed over the surface of the heat spreader within the first TIM; and
a heat sink disposed over the third TIM and fourth TIM.