Gate driving technique to lower switch on-resistance in switching converter applications
Techniques and apparatus for driving transistor gates of a switched-mode power supply (SMPS) circuit. One example power supply circuit generally includes a switching converter having a switching transistor and a gate driver having an output coupled to a gate of the switching transistor. The gate driver includes a first switching device coupled between the output of the gate driver and a first voltage rail; a second switching device coupled between the output of the gate driver and a voltage node of the gate driver; a third switching device coupled between the voltage node of the gate driver and a second voltage rail; and a voltage clamp coupled in series with a fourth switching device, the voltage clamp and the fourth switching device being coupled between a third voltage rail and the voltage node (or the output of the gate driver).
1. A power supply circuit comprising:
a switching converter having a switching transistor having a source coupled to a first voltage rail; and
a gate driver having an output coupled to a gate of the switching transistor, the gate driver comprising:
a first switching device coupled between the output of the gate driver and the first voltage rail;
a second switching device coupled between the output of the gate driver and a voltage node of the gate driver;
a third switching device coupled between the voltage node of the gate driver and a second voltage rail; and
a voltage clamp coupled in series with a fourth switching device, the voltage clamp and the fourth switching device being coupled between a third voltage rail and the voltage node, wherein:
the switching transistor is a p-type transistor;
the first voltage rail has a first voltage;
the second voltage rail has a second voltage lower than the first voltage; and
the third voltage rail has a third voltage lower than the second voltage.
2. The power supply circuit of claim 1 , wherein:
the first switching device comprises another p-type transistor; and
the second, third, and fourth switching devices comprise n-type transistors.
3. The power supply circuit of claim 1 , wherein the switching converter comprises an inverting buck-boost converter and wherein the switching transistor comprises a high-side p-type transistor in the inverting buck-boost converter.
4. The power supply circuit of claim 1 , wherein the switching converter comprises a charge pump with the switching transistor.
5. The power supply circuit of claim 1 , wherein the third switching device comprises an n-type transistor having a drain coupled to the second voltage rail and having a source coupled to the voltage node.
6. A power management integrated circuit (PMIC) comprising at least a portion of the power supply circuit of claim 1 .